Emil J. Tywoniak
90a2c92370
driver: allow --no-version still write things like Generated by Yosys
2025-05-07 11:34:23 +02:00
Emil J. Tywoniak
d7affb8821
driver: add --no-version to suppress writing Yosys version in command outputs
2025-05-05 13:12:08 +02:00
Jannis Harder
31d6d0ac17
formalff: Fix -declockgate test and missing emit for memories
2025-04-18 18:57:59 +02:00
Jannis Harder
b982da9f6a
formalff: Document -declockgate option
2025-04-18 17:44:39 +02:00
Jannis Harder
bd154a7188
formalff: Add -declockgate option
2025-04-18 17:44:34 +02:00
Krystine Sherwin
87d3b09988
cutpoint.cc: Fold -instances into -blackbox
...
Replace `cutpoint -blackbox` behaviour with `cutpoint -blackbox -instances` behaviour.
Drop `-instances` flag.
Add `-noscopeinfo` flag.
Use `RTLIL::Selection::boxed_module()` helper to shortcut blackbox check.
Update `cutpoint_blackbox.ys` tests to match.
2025-04-11 04:12:35 +12:00
Krystine Sherwin
8b1cc6e05e
cutpoint: Use new selection helpers
2025-04-11 04:12:34 +12:00
Krystine Sherwin
b705c546ea
cutpoint: Add -blackbox -instances
...
Replace module instances instead of module contents.
This fixes parametrisable width mismatch with read_verilog frontend, but not verific frontend.
2025-04-11 04:12:34 +12:00
Krystine Sherwin
ca57df8927
cutpoint: Add $scopeinfo cell
...
Also adds "blackbox" as a valid TYPE.
2025-04-11 04:12:34 +12:00
Krystine Sherwin
583771ef5b
cutpoint: Add -blackbox option
...
Replace the contents of all blackboxes in the design with a formal cut point.
Includes test script.
2025-04-11 04:12:34 +12:00
Krystine Sherwin
cd3b914132
Reinstate #4768
...
Revert the reversion so that we can fix the bugs that the PR missed.
2025-04-08 11:58:05 +12:00
Miodrag Milanović
d49364d96f
Revert "Refactor full_selection"
2025-04-07 12:11:55 +02:00
KrystalDelusion
98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections
...
Refactor full_selection
2025-04-05 14:15:27 +13:00
Emil J
ea74ad33a5
Merge pull request #4961 from YosysHQ/emil/cutpoint-typo
...
cutpoint: fix typo
2025-03-25 21:30:29 +01:00
Emil J. Tywoniak
4991ed9d4b
cutpoint: fix typo
2025-03-25 18:10:47 +01:00
Emil J. Tywoniak
4f3fdc8457
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
Krystine Sherwin
a3968d43f0
Drop deprecation on Design::selected_modules()
...
Instead, change the default `Design::selected_modules()` to match the behaviour (i.e. `selected_unboxed_modules_warn()`) because it's a lot of files to touch and they don't really _need_ to be updated.
Also change `Design::selected_whole_modules()` users over to `Design::selected_unboxed_whole_modules()`, except `attrmap` because I'm not convinced it should be ignoring boxes. So instead, leave the deprecation warning for that one use and come back to the pass another time.
2025-03-14 14:08:56 +13:00
Krystine Sherwin
dac2bb7d4d
Use selection helpers
...
Catch more uses of selection constructor without assigning a design.
2025-03-14 14:08:13 +13:00
Emil J. Tywoniak
a58481e9b7
mark all hash_into methods nodiscard
2025-01-14 12:39:15 +01:00
Emil J. Tywoniak
b9b9515bb0
hashlib: hash_eat -> hash_into
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854
hashlib: acc -> eat
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1
hashlib: redo interface for flexibility
2024-12-18 14:49:25 +01:00
Martin Povišer
1b1a6c4aed
Merge pull request #4525 from georgerennie/peepopt_clock_gate
...
peepopt: Add formal opt to rewrite latches to ffs in clock gates
2024-11-11 14:49:09 +01:00
Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
Emily Schmidt
bdb59ffc8e
add -fst-noinit flag to sim for not initializing the state from the fst file
2024-08-21 11:03:29 +01:00
George Rennie
236c69bed4
clk2fflogic: run peepopt -formalclk before processing design
...
* this attempts to rewrite clock gating patterns into a form that is
less likely to introduce combinational loops with clk2fflogic
* can be disabled with -nopeepopt which is useful for testing
clk2fflogic
2024-08-07 10:14:04 +01:00
Miodrag Milanovic
6d98418f3d
Set ranges on exported wires in VCD and FST
2024-08-02 15:23:00 +02:00
Martin Povišer
e063b96104
synthprop: Reformat the help
2024-07-25 11:43:58 +02:00
Jannis Harder
2bd889a59a
formalff -setundef: Fix handling for has_srst FFs
...
The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to
a copy and paste error.
This would crash when `has_ce` was false and could incorrectly determine
that an initial value is unused when `has_ce` and `has_srst` are both
set.
2024-04-15 11:53:30 +02:00
N. Engelhardt
d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops
...
celledges: support shift ops
2024-03-08 09:35:47 +01:00
Jannis Harder
bbdfcfdf30
clk2fflogic: Fix handling of $check cells
...
Fixes a bug in the handling of the recently introduced $check cells.
Both $check and $print cells in clk2fflogic are handled by the same code
and the existing tests for that were only using $print cells. This
missed a bug where the additional A signal of $check cells that is not
present on $print cells was dropped due to a typo, rendering $check
cells non-functional.
Also updates the tests to explicitly cover both cell types such that
they would have detected the now fixed bug.
2024-02-14 11:42:27 +01:00
Jannis Harder
e1a59ba80b
async2sync, clk2fflogic: Add support for $check and $print cells
2024-02-01 20:10:39 +01:00
Jannis Harder
7c818d30f7
sim: Bring $print trigger/sampling semantics in line with FFs
2024-01-25 16:21:03 +01:00
Martin Povišer
149bcd88ad
Merge pull request #4026 from uis246/fix-format
...
Fix printf formats
2024-01-15 16:04:11 +01:00
uis
5902b2826d
Fix printf formats
2024-01-15 12:07:54 +01:00
Dag Lem
acf916f654
Restore sim output from initial $display
2024-01-14 16:52:51 +01:00
Jannis Harder
57b4e16acd
sim: Include $display output in JSON summary
...
This allows tools like SBY to capture the $display output independent
from anything else sim might log. Additionally it provides source and
hierarchy locations for everything printed.
2024-01-11 12:01:39 +01:00
Martin Povišer
6581b5593c
sim: Print hierarchy for failed assertions
2023-12-06 12:09:07 +01:00
Claire Xen
a4951a3a97
Merge pull request #3986 from povik/sim-ui-fixes
...
Slightly improve `sim` UI
2023-10-16 16:54:05 +02:00
N. Engelhardt
6c562c76bc
fix handling right shifts
2023-10-12 11:46:09 +02:00
N. Engelhardt
3e22791810
Merge pull request #3975 from rmlarsen/optmerge
2023-10-09 17:05:19 +02:00
Martin Povišer
c3fd88624a
sim: Bail on processes
...
Instead of silently missimulating, error out when there are processes
found in the simulation hierarchy.
2023-10-05 19:25:17 +02:00
Martin Povišer
a782b15aae
sim: s/instanced/instantiated/
2023-10-05 19:25:17 +02:00
Martin Povišer
6ac43e49bc
sim: Change clocked read port suggestion to memory_nordff
...
`memory_nordff` has the advantage that it can be called just ahead of
the simulation step no matter whether the clocked read port has been
inferred or was explicitly instantiated in a flow.
2023-10-05 19:25:17 +02:00
Rasmus Munk Larsen
8e0308b5e7
Revert changes to celltypes.h. Use dict instead of std::unordered_map and most hash function for uint64_t to hashlib.h to support this.
2023-10-03 14:25:59 -07:00
Jannis Harder
7eaa4bcb46
sim: Add -noinitstate option and handle non-cosim initstate
...
This adds the -noinitstate option which is required to simulate
counterexamples to induction with yw-cosim. Also add handling for
$initstate cells for non-co-simulation.
2023-09-28 17:29:24 +02:00
Martin Povišer
5bef9b4e75
Merge pull request #3915 from povik/sim-print
...
sim: Add print support
2023-09-11 17:03:59 +02:00
Martin Povišer
d4d951657f
sim: Add -assert option to fail on failed assertions
2023-09-05 10:46:04 +02:00
Martin Povišer
50d117956c
sim: Add print support
2023-09-04 17:12:38 +02:00
Martin Povišer
f5485b59a9
sim: Bail if there are blackboxes in simulation
2023-07-20 21:01:03 +01:00
