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7496 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
bcd8027182 Also optimise MSB of $sub 2019-07-19 13:11:48 -07:00
Eddie Hung
5bd088a686 Add one more test with trimming Y_WIDTH of $sub 2019-07-19 13:11:30 -07:00
Eddie Hung
415a2716df Be more explicit 2019-07-19 12:53:18 -07:00
Eddie Hung
fc0e36d1c0 wreduce for $sub 2019-07-19 12:50:21 -07:00
Eddie Hung
4e9b1d36fa Add tests for sub too 2019-07-19 12:50:11 -07:00
Eddie Hung
3839bd50f2 Add test 2019-07-19 12:43:02 -07:00
Eddie Hung
25ff27e37f SigSpec::extract to take negative lengths 2019-07-19 12:34:04 -07:00
Eddie Hung
bba72f03dd Do not $mul -> $__mul if A and B are less than maxwidth 2019-07-19 11:54:26 -07:00
Eddie Hung
3dc3c749d5 Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold 2019-07-19 11:41:00 -07:00
Eddie Hung
1d14cec7fd Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too 2019-07-19 11:39:24 -07:00
Eddie Hung
9ad11ea2cc Fine tune ice40_dsp.pmg, add support for packing subsets of registers 2019-07-19 10:57:32 -07:00
Eddie Hung
8f0e796be1 Add support for ice40 signed multipliers 2019-07-19 10:38:13 -07:00
Eddie Hung
7bdb3996e2 Merge branch 'xc7dsp' into ice40dsp 2019-07-19 10:28:38 -07:00
Eddie Hung
ca94c2d3c4 Fix typo in B 2019-07-19 10:27:44 -07:00
Eddie Hung
d439a830c6 Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp 2019-07-19 09:40:47 -07:00
David Shah
80884d6f7b ice40: Fix test_dsp_model.sh 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:57 +01:00
David Shah
79f14c7514 ice40/cells_sim.v: Fix sign of J and K partial products 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:41 +01:00
Eddie Hung
2168568f43 Use sign_headroom instead 2019-07-19 09:16:13 -07:00
David Shah
3c84271543 ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:13:34 +01:00
Eddie Hung
171cd2ff73 Add tests for all combinations of A and B signedness for comb mul 2019-07-19 08:52:49 -07:00
Eddie Hung
f7753720fe Don't copy ref if exists already 2019-07-19 08:45:35 -07:00
Eddie Hung
bddd641290 Fix SB_MAC sim model -- do not sign extend internal products? 2019-07-18 21:03:54 -07:00
Eddie Hung
601fac97e4 Add params 2019-07-18 21:02:49 -07:00
Eddie Hung
a777be3091 Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 20:37:39 -07:00
Eddie Hung
0157043b97 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-07-18 20:36:48 -07:00
Eddie Hung
15c2a79ab9 Do not define `DSP_SIGNEDONLY macro if no exists 2019-07-18 16:04:58 -07:00
Eddie Hung
42e40dbd0a Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 15:45:25 -07:00
Eddie Hung
09411dd996 ice40_dsp to accept $__MUL16X16 too 2019-07-18 15:38:28 -07:00
Eddie Hung
266c1ae122 synth_ice40 to decompose into 16x16 2019-07-18 15:38:09 -07:00
Eddie Hung
2339b7fc37 mul2dsp to create cells that can be interchanged with $mul 2019-07-18 15:37:35 -07:00
Eddie Hung
802470746c Check if RHS is empty first 2019-07-18 15:22:00 -07:00
Eddie Hung
e22a752242 Make consistent 2019-07-18 15:21:23 -07:00
Eddie Hung
90ac147eb2 Do not autoremove ffP aor muxP 2019-07-18 15:02:41 -07:00
Eddie Hung
43616e1414 Update Makefile too 2019-07-18 14:51:55 -07:00
Eddie Hung
4b71e6c421 Add CHANGELOG entry 2019-07-18 14:21:04 -07:00
Eddie Hung
b97fe6e866 Work in progress for renaming labels/options in synth_xilinx 2019-07-18 14:20:43 -07:00
Eddie Hung
08fe63c61e Improve pattern matcher to match subsets of $dffe? cells 2019-07-18 14:08:18 -07:00
Eddie Hung
79d63479ea Improve A/B reg packing 2019-07-18 13:30:35 -07:00
Eddie Hung
e075f0dda0 Do not autoremove A/B registers since they might have other consumers 2019-07-18 13:22:22 -07:00
Eddie Hung
0727b2c902 Fix xilinx_dsp index cast 2019-07-18 13:18:04 -07:00
Eddie Hung
8326af5418 Fix signed multiplier decomposition 2019-07-18 13:11:26 -07:00
Eddie Hung
5562cb08a4 Use single DSP_SIGNEDONLY macro 2019-07-18 13:09:55 -07:00
David Shah
9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups 
Assorted synth_intel cleanups from @bwidawsk
 2019-07-18 19:04:28 +01:00
Dan Ravensloft
0c999ac2c4 synth_intel: Use stringf 2019-07-18 19:02:23 +01:00
Eddie Hung
2024357f32 Working for unsigned 2019-07-18 10:53:18 -07:00
David Shah
8e0f7c18f1
Merge pull request #1207 from ZirconiumX/intel_new_pass_names 
synth_intel: rename for consistency with #1184
 2019-07-18 17:34:55 +01:00
Dan Ravensloft
50f5e29724 synth_intel: s/not family/no family/ 2019-07-18 17:28:21 +01:00
Eddie Hung
d5cd2c80be Cleanup 2019-07-18 09:20:48 -07:00
Dan Ravensloft
d5b3b3bc6f synth_intel: revert change to run_max10 2019-07-18 17:09:15 +01:00
Ben Widawsky
999811572a intel_synth: Fix help message 
cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.

Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-07-18 17:06:25 +01:00