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Code Activity
4818 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Clifford Wolf
f3983a0940 Also escape "=" in spice output 2016-05-20 16:43:13 +02:00
Clifford Wolf
060bf4819a Small improvements in Verilog front-end docs 2016-05-20 16:21:35 +02:00
Kaj Tuomi
8c3bc2ac0d Close opened dump file. 2016-05-19 11:53:29 +03:00
Kaj Tuomi
f6221ade95 Fix for Modelsim transcript line warp issue #164 2016-05-19 11:34:38 +03:00
Clifford Wolf
ffcdc53a18 Don't sign-extend memory bram initialization data 2016-05-15 00:05:30 +02:00
Clifford Wolf
864eeadcd9 Added missing "#define HASHLIB_H" 2016-05-14 11:43:20 +02:00
Clifford Wolf
d05115ceda Minor presentation fixes 2016-05-14 11:35:39 +02:00
Clifford Wolf
407cdea0bc Updated min GCC requirement to GCC 4.8 2016-05-11 09:31:53 +02:00
Clifford Wolf
b8b39472bb Added manual download link to README 2016-05-09 12:43:49 +02:00
Clifford Wolf
570014800a Include <cmath> in yosys.h 2016-05-08 10:50:39 +02:00
Clifford Wolf
fa76d51941 Merge pull request #162 from azonenberg/master 
Added GP_DELAY cell. Fixed several errors in simulation models.
 2016-05-08 10:22:01 +02:00
Andrew Zonenberg
47eace0b9f Added GP_DELAY cell 2016-05-07 21:29:26 -07:00
Andrew Zonenberg
41bbad4e4c Fixed typo in port name 2016-05-07 21:14:42 -07:00
Andrew Zonenberg
b5171541cd Fixed extra semicolon 2016-05-07 21:14:18 -07:00
Andrew Zonenberg
85ee88b0ee Fixed typo in parameter name 2016-05-07 21:14:00 -07:00
Andrew Zonenberg
a0c19aae55 Added simulation timescale declaration 2016-05-07 21:13:47 -07:00
Clifford Wolf
f103bfb9ba Fixes for MXE build 2016-05-07 10:53:18 +02:00
Clifford Wolf
c3f6e0ea85 Added support for "keep" attribute to shregmap 2016-05-07 09:33:16 +02:00
Clifford Wolf
6fe3d5a1cf Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
Clifford Wolf
d10dfccabb Added "write_blif -noalias" 2016-05-06 15:05:53 +02:00
Clifford Wolf
126da0ad3d Fixed ice40_opt lut unmapping, added "ice40_opt -unlut" 2016-05-06 14:32:32 +02:00
Clifford Wolf
aadca148da Fixed preservation of important attributes in techmap 2016-05-06 13:59:30 +02:00
Clifford Wolf
ec1938737b Merge pull request #159 from azonenberg/master 
Fixes to use new I/O pad techmapping, renamed ports for GP_SHREG
 2016-05-05 18:18:48 +02:00
Andrew Zonenberg
2096a05ec2 Changed order of passes for better handling of INIT attributes on "output reg" FFs 2016-05-04 17:13:54 -07:00
Andrew Zonenberg
3486637b19 Changed port names in greenpak shregmap 2016-05-04 17:04:50 -07:00
Andrew Zonenberg
dee1c27a19 Renamed module parameter 2016-05-04 17:03:45 -07:00
Andrew Zonenberg
a613f171ae Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract 2016-05-04 15:55:16 -07:00
Clifford Wolf
9647dc3c07 Added tristate buffer support to iopadmap 2016-05-04 22:48:02 +02:00
Clifford Wolf
86add29072 Merge pull request #157 from azonenberg/master 
Added GP_ABUF cell, support for tri-state I/O buffers in GreenPak
 2016-05-04 19:12:59 +02:00
Andrew Zonenberg
deb1eccab5 Fixed incorrect signal naming in GP_IOBUF 2016-05-04 08:06:18 -07:00
Andrew Zonenberg
2db8dd6d35 Merge https://github.com/cliffordwolf/yosys 2016-05-04 07:23:27 -07:00
Clifford Wolf
7a74ae4c54 Merge branch 'master' of github.com:cliffordwolf/yosys 2016-05-04 10:48:42 +02:00
Clifford Wolf
658f93663b Fixed iopadmap attribute handling 2016-05-04 10:48:23 +02:00
Andrew Zonenberg
dcee3256d5 Added tri-state I/O extraction for GreenPak 2016-05-03 22:53:29 -07:00
Andrew Zonenberg
66095153fd Added GreenPak I/O buffer cells 2016-05-03 22:03:04 -07:00
Andrew Zonenberg
9fc9d5f1fb Added comment to clarify GP_ABUF cell 2016-05-02 20:29:39 -07:00
Andrew Zonenberg
79460208c9 Added GP_ABUF cell 2016-05-02 20:27:41 -07:00
Clifford Wolf
12000b90de Merge pull request #154 from azonenberg/master 
Add GP_PGA cell
 2016-05-02 09:49:07 +02:00
Andrew Zonenberg
3a85e40f42 Merge https://github.com/cliffordwolf/yosys 2016-05-01 10:07:21 -07:00
Clifford Wolf
06d35ea942 Improved TCL_VERSION detection so it does not read .tclshrc 2016-04-29 10:26:22 +02:00
Andrew Zonenberg
fb87022dca Merge https://github.com/cliffordwolf/yosys 2016-04-29 00:57:37 -07:00
Clifford Wolf
e01464e2ac Added "qwp -v" 2016-04-28 23:17:30 +02:00
Andrew Zonenberg
134e093e4e Added GP_PGA cell 2016-04-27 23:07:21 -07:00
Clifford Wolf
0d2923cccd Connections between inputs and inouts are driven by the input 2016-04-26 19:49:05 +02:00
Clifford Wolf
958fb29c76 Fixed test_autotb for modules with many cell ports 2016-04-25 16:37:11 +02:00
Clifford Wolf
93e107e455 Fixed proc_mux performance bug 2016-04-25 10:43:04 +02:00
Clifford Wolf
d086224a39 Merge pull request #150 from azonenberg/master 
GreenPak analog comparator support
 2016-04-25 10:33:18 +02:00
Andrew Zonenberg
d57c85111f Merge https://github.com/cliffordwolf/yosys 2016-04-24 22:11:56 -07:00
Andrew Zonenberg
349d717202 Removed VIN_BUF_EN 2016-04-24 17:01:21 -07:00
Clifford Wolf
b1d6f05fa2 Fixed performance bug in proc_dlatch 2016-04-24 19:29:56 +02:00