Felix Vietmeyer
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a71c38f163
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Add note about test requirements in README
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2019-03-16 06:20:59 -06:00 |
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Eddie Hung
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29a8d4745e
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Cleanup synth_xilinx
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2019-03-15 23:01:40 -07:00 |
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Eddie Hung
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06f8f2654a
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Working
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2019-03-15 19:13:40 -07:00 |
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Clifford Wolf
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aa65d3fe65
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Improve mix of src/wire/wirebit coverage in "mutate -list"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-16 00:55:46 +01:00 |
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Clifford Wolf
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3fb363ec8c
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Merge pull request #876 from YosysHQ/clifford/fmcombine
Add fmcombine pass
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2019-03-16 00:17:15 +01:00 |
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Clifford Wolf
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dacaebae35
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Add "fmcombine -fwd -bwd -nop"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-15 21:45:37 +01:00 |
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Clifford Wolf
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370db33a4c
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Add fmcombine pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-15 20:46:17 +01:00 |
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Clifford Wolf
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b5cf8c9442
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Merge pull request #875 from YosysHQ/clifford/mutate
Add "mutate" pass
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2019-03-15 00:51:40 +01:00 |
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Clifford Wolf
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9820ed6531
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Disable realmath tests
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-15 00:48:23 +01:00 |
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Clifford Wolf
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d1985f6a22
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Improvements in "mutate" list-reduce algorithm
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-15 00:18:31 +01:00 |
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Clifford Wolf
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27a5d9c91e
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Add "mutate -cfg", improve pick_cover behavior
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 23:20:41 +01:00 |
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Clifford Wolf
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4d304e3da7
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Add a strictly coverage-driven mutation selection strategy
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 23:01:55 +01:00 |
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Clifford Wolf
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2a4263a75d
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Improve "mutate" wire coverage metric
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 23:01:01 +01:00 |
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Clifford Wolf
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1b4fdbb0d8
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Add more mutation types, improve mutation src cover
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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bacca57537
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Fix smtbmc.py handling of zero appended steps
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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6ad5d036c5
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Add "mutate" command DB reduce functionality
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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76c9c350e7
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Add hashlib "<container>::element(int n)" methods
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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8e6b69d7bb
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Add "mutate -mode inv", various other mutate improvements
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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ea8ee24140
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Add basic "mutate -list N" framework
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 22:04:42 +01:00 |
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Clifford Wolf
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c4575103af
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Merge pull request #874 from YosysHQ/clifford/andopt
Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
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2019-03-14 21:22:16 +01:00 |
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Clifford Wolf
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f806b95ed6
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Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 20:52:00 +01:00 |
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Clifford Wolf
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44a44a06ed
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Merge pull request #872 from YosysHQ/clifford/pmuxfix
Improve handling of "full_case" attributes
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2019-03-14 18:42:45 +01:00 |
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Clifford Wolf
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17caaa3fa8
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Improve handling of "full_case" attributes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 17:51:21 +01:00 |
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Clifford Wolf
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04e920337b
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Fix a syntax bug in ilang backend related to process case statements
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-14 17:50:20 +01:00 |
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Eddie Hung
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e7ef7fa443
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Reverse bits in INIT parameter for Xilinx, since MSB is shifted first
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2019-03-14 09:38:42 -07:00 |
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Eddie Hung
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af5706c2a3
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Misspell
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2019-03-14 09:06:56 -07:00 |
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Eddie Hung
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8af9979aab
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Revert "Add shregmap -init_msb_first and use in synth_xilinx"
This reverts commit 26ecbc1aee.
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2019-03-14 09:01:48 -07:00 |
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Eddie Hung
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f1a8e8a480
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Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-14 08:59:19 -07:00 |
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Clifford Wolf
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53b28b3f01
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Merge pull request #869 from cr1901/win-shell
Install launcher executable when running yosys-smtbmc on Windows.
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2019-03-14 16:43:23 +01:00 |
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Eddie Hung
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26ecbc1aee
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Add shregmap -init_msb_first and use in synth_xilinx
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2019-03-14 08:10:02 -07:00 |
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Eddie Hung
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79b4a275ce
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Fix cells_map for SRL
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2019-03-14 08:09:48 -07:00 |
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Eddie Hung
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edca2f1163
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Move shregmap until after first techmap
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2019-03-13 17:13:52 -07:00 |
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Eddie Hung
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24f129ddfb
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Refactor $__SHREG__ in cells_map.v
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2019-03-13 16:17:54 -07:00 |
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William D. Jones
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ff15cf9b1f
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Install launcher executable when running yosys-smtbmc on Windows.
Signed-off-by: William D. Jones <thor0505@comcast.net>
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2019-03-13 13:49:16 -04:00 |
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Clifford Wolf
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f0b2d8e467
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Merge pull request #868 from YosysHQ/clifford/fixmem
Various mem2reg-related improvements in handling of memories
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2019-03-13 13:40:30 +01:00 |
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Clifford Wolf
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1cd04a6838
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Fix a bug in handling quotes in multi-cmd lines in Yosys scripts
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-12 21:15:11 +01:00 |
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Clifford Wolf
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ac10f72e49
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Merge pull request #866 from YosysHQ/clifford/idstuff
Improve determinism of IdString DB for similar scripts
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2019-03-12 20:27:36 +01:00 |
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Clifford Wolf
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9284cf92b8
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Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-12 20:14:18 +01:00 |
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Clifford Wolf
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d25a0c8ade
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Improve handling of memories used in mem index expressions on LHS of an assignment
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-12 20:12:02 +01:00 |
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Clifford Wolf
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a4ddc569b4
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Remove outdated "blocking assignment to memory" warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-12 20:10:55 +01:00 |
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Clifford Wolf
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ab5b50ae3c
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Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-12 20:09:47 +01:00 |
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Clifford Wolf
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20c6a8c9b0
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Improve determinism of IdString DB for similar scripts
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-11 20:12:28 +01:00 |
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Eddie Hung
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ef48b62cb1
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Merge pull request #864 from YosysHQ/svalabelfix
Fix handling of cases that look like sva labels, fixes #862
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2019-03-11 11:58:07 -07:00 |
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Clifford Wolf
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d9bb5f3637
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Add ENABLE_GLOB Makefile switch
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-11 01:08:36 -07:00 |
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Clifford Wolf
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b02d9c2634
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Fix handling of cases that look like sva labels, fixes #862
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-10 16:27:18 -07:00 |
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Clifford Wolf
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ff4c2a14ae
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Fix typo in ice40_braminit help msg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-09 13:24:55 -08:00 |
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Clifford Wolf
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2ace1b0041
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Merge pull request #859 from smunaut/ice40_braminit
iCE40 BRAM primitives init from file
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2019-03-09 13:24:10 -08:00 |
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Clifford Wolf
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94f995ee37
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Fix signed $shift/$shiftx handling in write_smt2
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-09 13:19:41 -08:00 |
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Clifford Wolf
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399ab16315
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Add $dffsr support to async2sync
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-09 11:52:00 -08:00 |
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Clifford Wolf
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cebd21aa96
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Merge pull request #858 from YosysHQ/clifford/svalabels
Add support for using SVA labels in yosys-smtbmc console output
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2019-03-09 11:14:57 -08:00 |
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