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Merge pull request from YosysHQ/clifford/andopt

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Improve handling of and-with-1 and or-with-0 in opt_expr, fixes
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Clifford Wolf 2019-03-14 21:22:16 +01:00 committed by GitHub
parent 44a44a06ed f806b95ed6
commit c4575103af
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1 changed files with 7 additions and 0 deletions

7
passes/opt/opt_expr.cc
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@ -155,6 +155,13 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
new_b.append_bit(it.first.second);
}
if (cell->type.in("$and", "$or") && i == GRP_CONST_A) {
log(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
module->connect(new_y, new_b);
module->connect(new_conn);
continue;
}
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
c->setPort("\\A", new_a);