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Code Activity
8435 commits 122 branches 59 tags 72 MiB
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288 commits

Author SHA1 Message Date
Eddie Hung
c0b99ed0e8 Do not overwrite LUT param 2019-08-28 18:45:09 -07:00
Eddie Hung
070f3ac561 Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival 2019-08-28 17:29:25 -07:00
Eddie Hung
d46d38e4d5 Trailing comma 2019-08-28 17:25:54 -07:00
Eddie Hung
f5b4bc847c Adapt to $__ICE40_CARRY_WRAPPER 2019-08-28 17:25:05 -07:00
Eddie Hung
e569f13870 Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" 
This reverts commit 2aedee1f0e.
 2019-08-28 17:22:44 -07:00
Eddie Hung
2421cb3fed Add arrival times for HX devices 2019-08-28 17:21:37 -07:00
Eddie Hung
e4f89e01b5 Specify ice40 family to cells_sim.v using define 2019-08-28 17:21:12 -07:00
Eddie Hung
2aedee1f0e Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with 
CARRY_WRAPPER in the same way since I0 and I3 could be used
 2019-08-28 17:07:36 -07:00
Eddie Hung
077e9d4ada Update box size and timings 2019-08-28 17:07:24 -07:00
Eddie Hung
129df7184a Update to new $__ICE40_CARRY_WRAPPER 2019-08-28 17:07:07 -07:00
Eddie Hung
a270af00cc Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 
Refactor abc9 to use port attributes, not module attributes
 2019-08-20 11:59:31 -07:00
Eddie Hung
d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00
Eddie Hung
1c57b1e7ea Update abc_* attr in ecp5 and ice40 2019-08-16 15:56:57 -07:00
Eddie Hung
8a2480526f Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER 2019-08-12 12:19:25 -07:00
Eddie Hung
12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
Eddie Hung
f890cfb63b Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Eddie Hung
6d254f2de8 Add wreduce to synth_ice40 -dsp as well 2019-08-09 17:05:56 -07:00
Eddie Hung
2c0be7aa5d Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing 2019-08-08 12:56:05 -07:00
Eddie Hung
9776084eda Allow whitebox modules to be overwritten 2019-08-07 16:40:24 -07:00
Eddie Hung
675c1d4218 Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
Eddie Hung
cc331cf70d Add test 2019-08-07 16:29:38 -07:00
Eddie Hung
ea8ac8fd74 Remove ice40_unlut 2019-08-07 16:29:38 -07:00
Eddie Hung
6b314c8371 Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER 2019-08-07 16:29:38 -07:00
Eddie Hung
a206aed977 Run "opt_expr -fine" instead of "wreduce" due to #1213 2019-08-07 13:59:07 -07:00
Eddie Hung
6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung
48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Eddie Hung
915f4e34bf DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH 2019-08-01 13:20:34 -07:00
Eddie Hung
cb505c50d3 Remove debug 2019-07-22 16:14:15 -07:00
Eddie Hung
4d71ab384d Rename according to vendor doc TN1295 2019-07-22 15:08:26 -07:00
Eddie Hung
5e70b8a22b opt and wreduce necessary for -dsp 2019-07-22 13:48:33 -07:00
Eddie Hung
47fd042b9f Indirection via $__soft_mul 2019-07-19 20:20:33 -07:00
Eddie Hung
3dc3c749d5 Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold 2019-07-19 11:41:00 -07:00
Eddie Hung
d439a830c6 Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp 2019-07-19 09:40:47 -07:00
David Shah
80884d6f7b ice40: Fix test_dsp_model.sh 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:57 +01:00
David Shah
79f14c7514 ice40/cells_sim.v: Fix sign of J and K partial products 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:41 +01:00
David Shah
3c84271543 ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:13:34 +01:00
Eddie Hung
171cd2ff73 Add tests for all combinations of A and B signedness for comb mul 2019-07-19 08:52:49 -07:00
Eddie Hung
f7753720fe Don't copy ref if exists already 2019-07-19 08:45:35 -07:00
Eddie Hung
bddd641290 Fix SB_MAC sim model -- do not sign extend internal products? 2019-07-18 21:03:54 -07:00
Eddie Hung
42e40dbd0a Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 15:45:25 -07:00
Eddie Hung
266c1ae122 synth_ice40 to decompose into 16x16 2019-07-18 15:38:09 -07:00
Clifford Wolf
e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels 
synth_{ice40,ecp5}: more sensible pass label naming
 2019-07-18 15:34:28 +02:00
Sylvain Munaut
f28e38de99 ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map 
The new mapping introduced in 437fec0d88
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-07-16 23:57:15 +02:00
whitequark
ba099bfe9b synth_{ice40,ecp5}: more sensible pass label naming. 2019-07-16 20:41:51 +00:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix 
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
 2019-07-16 08:52:14 -07:00
Eddie Hung
5fb27c071b $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00