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yosys/techlibs/ice40
2019-08-28 17:21:12 -07:00
..
tests
.gitignore
abc_hx.box Update box size and timings 2019-08-28 17:07:24 -07:00
abc_hx.lut
abc_lp.box Update box size and timings 2019-08-28 17:07:24 -07:00
abc_lp.lut
abc_u.box Update box size and timings 2019-08-28 17:07:24 -07:00
abc_u.lut
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v
cells_sim.v
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with 2019-08-28 17:07:36 -07:00
latches_map.v
Makefile.inc
synth_ice40.cc Specify ice40 family to cells_sim.v using define 2019-08-28 17:21:12 -07:00