Robert O'Callahan
8b75c06141
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
Jannis Harder
4b273a4ae9
share: Cleanup and additional testing
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Fixes a typo and adds another test case that triggers the fallback
behavior as the existing tests all trigger the new optimization.
2025-04-15 12:34:46 +02:00
Emil J. Tywoniak
6240aec433
test: restore verific handling, nicer naming
2024-12-13 10:24:47 +01:00
Krystine Sherwin
ee73a91f44
Remove references to ilang
2024-11-05 12:36:31 +13:00
Dag Lem
e0d3977e19
Add support for $dimensions and $unpacked_dimensions
2024-02-11 11:26:52 -05:00
Dag Lem
2125357e76
Add support for $increment
2024-02-11 11:26:52 -05:00
Dag Lem
39fea32c6e
Add support for packed multidimensional arrays
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* Generalization of dimensions metadata (also simplifies $size et al.)
* Parsing and elaboration of multidimensional packed ranges
2024-02-11 11:26:52 -05:00
Jannis Harder
331ac5285f
tests: Run async2sync before sat and/or sim to handle $check cells
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Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.
While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.
2024-02-01 16:14:11 +01:00
Miodrag Milanovic
27c5bafc95
Proper example code
2022-03-14 15:39:11 +01:00
Miodrag Milanovic
6db23de7b1
bug fix and cleanups
2022-02-04 10:01:06 +01:00
Miodrag Milanovic
7ef6da4c7d
Add test cases for co-simulation
2022-02-02 13:22:44 +01:00
Marcelina Kościelnicka
4746ffd7b2
assertpmux: Fix crash on unused $pmux output.
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Fixes #2595 .
2021-02-22 23:30:28 +01:00
clairexen
7e2fc2eaeb
Merge pull request #2378 from udif/pr_dollar_high_low
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Added $high(), $low(), $left(), $right()
2020-10-01 18:17:36 +02:00
Xiretza
bed14241ef
tests: add gitignores for auto-generated makefiles
2020-09-26 16:28:24 +02:00
Xiretza
acd47bbd52
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
Udi Finkelstein
7ed0e23e19
We can now handle array slices (e.g. $size(x[1]) etc. )
2020-09-17 00:55:17 +03:00
Udi Finkelstein
b548722bee
Added $high(), $low(), $left(), $right()
2020-09-15 20:49:52 +03:00
Marcelina Kościelnicka
0c6d0d4b5d
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
2020-07-24 03:19:21 +02:00
Eddie Hung
5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631
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clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-02-05 19:31:18 +01:00
Eddie Hung
2245afa142
More rigorous test
2020-01-16 09:15:42 -08:00
Eddie Hung
e30b6bbbf8
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-01-15 09:51:31 -08:00
Eddie Hung
4a80510877
Even more obvious testcase
2019-12-11 23:52:05 -08:00
Eddie Hung
61a1f3f49b
Make testcase clearer with \o having its own init
2019-12-11 23:48:09 -08:00
Eddie Hung
e75ca29b19
Add test: 'Warning: ignoring initial value on non-register: \o'
2019-12-11 11:26:54 -08:00
Eddie Hung
3fb604c75d
Revert "Add test that is expecting to fail"
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This reverts commit c28d4b8047
2019-10-08 12:41:26 -07:00
Eddie Hung
c28d4b8047
Add test that is expecting to fail
2019-10-02 14:52:40 -07:00
Eddie Hung
00387f3927
Revert to using clean
2019-08-27 09:24:32 -07:00
Eddie Hung
dc87372a97
Wire with init on FF part, 1'bx on non-FF part
2019-08-24 15:05:44 -07:00
Eddie Hung
10c41a5cf5
Blocking assignment
2019-08-23 09:11:04 -07:00
Eddie Hung
51ffb093b5
In sat: 'x' in init attr should not override constant
2019-08-22 16:43:08 -07:00
Zachary Snow
5855024ccc
support repeat loops with constant repeat counts outside of constant functions
2019-04-09 12:28:32 -04:00
Clifford Wolf
dbfd8460a9
Allow $size and $bits in verilog mode, actually check test case
2017-09-29 11:56:43 +02:00
Clifford Wolf
8836943693
Added yet another resource sharing test case
2014-07-20 21:15:01 +02:00
Clifford Wolf
3b52121d32
now ignore init attributes on non-register wires in sat command
2014-07-05 11:18:38 +02:00
Clifford Wolf
482d9208aa
Added read_verilog -sv options, added support for bit, logic,
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allways_ff, always_comb, and always_latch
2014-06-12 11:54:20 +02:00
Clifford Wolf
039bb456cc
Added test cases for expose -evert-dff
2014-02-08 21:31:56 +01:00
Clifford Wolf
244e8ce1f4
Added splice command
2014-02-07 20:30:56 +01:00
Clifford Wolf
849fd62cfe
Added counters sat test case
2014-02-06 01:00:56 +01:00
Clifford Wolf
7a66b38c3e
Added test cases for sat command
2014-02-04 13:43:34 +01:00
