Eddie Hung
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2b350401c4
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Fix spacing from spaces to tabs
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2019-06-07 15:44:57 -07:00 |
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Clifford Wolf
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7395a80690
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Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger
Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
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2019-06-07 23:13:34 +02:00 |
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Eddie Hung
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f48c6920b7
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Add read_aiger to CHANGELOG
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2019-06-07 13:12:48 -07:00 |
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Eddie Hung
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6934f4bdd5
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Fix spacing (entire file is wrong anyway, will fix later)
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2019-06-07 11:30:36 -07:00 |
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Eddie Hung
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d00ae1d6a8
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Remove unnecessary std::getline() for ASCII
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2019-06-07 11:28:25 -07:00 |
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Eddie Hung
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65924fd12f
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Test *.aag too, by using *.aig as reference
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2019-06-07 11:28:05 -07:00 |
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Eddie Hung
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a04521c6b7
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Fix read_aiger -- create zero driver, fix init width, parse 'b'
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2019-06-07 11:07:15 -07:00 |
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Eddie Hung
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abc40924ed
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Use ABC to convert from AIGER to Verilog
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2019-06-07 11:06:57 -07:00 |
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Eddie Hung
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ebe29b6659
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Use ABC to convert AIGER to Verilog, then sat against Yosys
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2019-06-07 11:05:36 -07:00 |
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Eddie Hung
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1b113a0574
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Add symbols to AIGER test inputs for ABC
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2019-06-07 11:05:25 -07:00 |
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Clifford Wolf
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6d49145497
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Merge pull request #1077 from YosysHQ/clifford/pr983
elaboration system tasks
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2019-06-07 13:39:46 +02:00 |
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Clifford Wolf
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f01a61f093
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Rename implicit_ports.sv test to implicit_ports.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-07 13:12:25 +02:00 |
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Clifford Wolf
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211d85cfcc
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Fixes and cleanups in AST_TECALL handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-07 12:41:09 +02:00 |
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Clifford Wolf
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a3bbc5365b
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Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
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2019-06-07 12:08:42 +02:00 |
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Clifford Wolf
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169de05f3b
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Merge branch 'tux3-implicit_named_connection'
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2019-06-07 11:53:46 +02:00 |
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Clifford Wolf
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7116621d22
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Merge pull request #1076 from thasti/centos7-build-fix
Fix pyosys-build on CentOS7
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2019-06-07 11:48:33 +02:00 |
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Clifford Wolf
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a0b57f2a6f
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Cleanup tux3-implicit_named_connection
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-07 11:46:16 +02:00 |
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Clifford Wolf
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b637b3109d
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Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection
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2019-06-07 11:41:54 +02:00 |
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Stefan Biereigel
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d018e02614
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remove boost/log/exceptions.hpp from wrapper generator
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2019-06-07 09:47:33 +02:00 |
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tux3
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88f5977093
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SystemVerilog support for implicit named port connections
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
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2019-06-06 18:07:49 +02:00 |
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Clifford Wolf
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b894187cf6
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Merge pull request #1060 from antmicro/parsing_attr_on_port_conn
Added support for parsing attributes on port connections.
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2019-06-06 12:34:05 +02:00 |
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David Shah
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30cedaca10
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Merge pull request #1073 from whitequark/ecp5-diamond-iob
ECP5: implement most Diamond I/O buffer primitives
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2019-06-06 11:22:49 +01:00 |
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whitequark
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f3a26730b6
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ECP5: implement all Diamond I/O buffer primitives.
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2019-06-06 10:18:33 +00:00 |
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Clifford Wolf
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e4e1cd6930
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Merge pull request #1071 from YosysHQ/eddie/fix_1070
Fix typo in opt_rmdff causing register to be incorrectly removed
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2019-06-06 06:50:12 +02:00 |
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Clifford Wolf
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50e2dce5e7
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Merge pull request #1072 from YosysHQ/eddie/fix_1069
Error out if no top module given before 'sim'
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2019-06-06 06:49:07 +02:00 |
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Eddie Hung
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fd8ef128bf
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Missing doc for -tech xilinx in shregmap
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2019-06-05 14:21:44 -07:00 |
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Eddie Hung
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dd134914cc
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Error out if no top module given before 'sim'
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2019-06-05 14:16:24 -07:00 |
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Eddie Hung
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feb2ddb52b
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Fix typo in opt_rmdff
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2019-06-05 14:08:14 -07:00 |
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Eddie Hung
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a3a80b755c
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Merge pull request #1067 from YosysHQ/clifford/fix1065
Suppress driver-driver conflict warning for unknown cell types
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2019-06-05 09:59:05 -07:00 |
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Maciej Kurc
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03e0d3a17c
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Fixed memory leak.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-06-05 10:42:43 +02:00 |
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Clifford Wolf
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f15b5e6309
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Merge pull request #1066 from YosysHQ/clifford/fix1056
Remove yosys_banner() from python wrapper init
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2019-06-05 10:37:39 +02:00 |
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Clifford Wolf
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b33176dafb
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Major rewrite of wire selection in setundef -init
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 10:26:48 +02:00 |
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Clifford Wolf
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6cc60ffd67
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Indent fix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 09:53:06 +02:00 |
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Clifford Wolf
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00d32eb73d
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Merge pull request #999 from jakobwenzel/setundefInitFix
initialize more registers in setundef -init
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2019-06-05 09:50:15 +02:00 |
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Clifford Wolf
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4190d7c094
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Fix typo in fmcombine log message, fixes #1063
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 09:26:44 +02:00 |
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Clifford Wolf
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8a6f9977f6
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Suppress driver-driver conflict warning for unknown cell types, fixes #1065
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 09:14:12 +02:00 |
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Clifford Wolf
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dd3c333c0a
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Remove yosys_banner() from python wrapper init, fixes #1056
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 08:57:33 +02:00 |
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Clifford Wolf
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1332051f33
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Merge pull request #1062 from tux3/patch-1
README.md: Missing formatting for <tag>
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2019-06-04 14:37:10 +02:00 |
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Tux3
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c66d644b66
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README.md: Missing formatting for <tag>
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2019-06-04 10:45:41 +02:00 |
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Maciej Kurc
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b79bd5b3ca
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-06-04 10:42:42 +02:00 |
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Eddie Hung
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1217e47e83
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Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map
Execute techmap and arith_map simultaneously
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2019-06-03 20:23:37 -07:00 |
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Eddie Hung
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02973474df
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Remove extra newline
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2019-06-03 20:04:47 -07:00 |
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Eddie Hung
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0ad50332d9
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Execute techmap and arith_map simultaneously
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2019-06-03 19:36:09 -07:00 |
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Maciej Kurc
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5739cf5265
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Added tests for attributes
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-06-03 09:25:20 +02:00 |
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Clifford Wolf
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36120fcc30
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Only support Symbiotic EDA flavored Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-02 10:14:50 +02:00 |
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Maciej Kurc
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a6cadf6318
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Added support for parsing attributes on port connections.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-05-31 14:58:43 +02:00 |
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Clifford Wolf
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90ec2cda42
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Fix "tee" handling of log_streams
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-31 09:28:51 +02:00 |
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Clifford Wolf
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2faa1d0e80
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Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-30 10:04:26 +02:00 |
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Clifford Wolf
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0df8a3b461
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Merge pull request #1057 from mmicko/fix_478
Aded one more load of .conf to support change of prefix
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2019-05-30 09:58:51 +02:00 |
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Miodrag Milanovic
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14bd40cd3d
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Aded one more load of .conf to support change of prefix
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2019-05-29 18:57:03 +02:00 |
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