mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-28 10:19:26 +00:00
Code Activity
9974 commits 121 branches 59 tags 72 MiB
Commit graph

9974 commits

This branch
This branch
All branches
Author SHA1 Message Date
Alberto Gonzalez
26bd686259
glift: Add -instrument-more option to add 4 more versions of taint tracking logic. Also refactor a bit and update help text. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez
bc207d5426
glift: Change command names to better represent their functions. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez
ddfb9f08e2
glift: Add -create-imprecise command, rename other commands, and re-work the help text. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez
ca3844d44e
glift: Add examples, including a number of benchmarks used in some academic works. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez
72cebef279
glift: Add replacement scoring and area minimization option. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez
c36440a7ee
glift: Remove outputs by default; add -keep-outputs option; properly reset internal state between calls. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez
19dafcd4f1
glift: Initial implementation of the -sketchify option. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez
09848b3b9f
glift: Initial implementation of GLIFT model construction. 2020-07-01 19:51:45 +00:00
Alberto Gonzalez
5f45fe51ea
glift: Add skeleton for glift command. 2020-07-01 19:51:45 +00:00
clairexen
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar 
Signed and macro grammar update
 2020-07-01 16:41:32 +02:00
clairexen
8ce4f8790e
Merge pull request #2179 from splhack/static-cast 
Support SystemVerilog Static Cast
 2020-07-01 16:40:20 +02:00
clairexen
b1707407a0
Merge pull request #2138 from boqwxp/qbfsat-oflag 
qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC
 2020-07-01 16:35:27 +02:00
clairexen
2b0f6e24e2
Merge pull request #2206 from boqwxp/qbfsat-fix-name-specialization 
qbfsat: Fix name-based hole specialization
 2020-07-01 16:34:32 +02:00
clairexen
9d658a1970
Merge pull request #2136 from zachjs/master 
Allow constant function calls in for loops and generate if and case
 2020-06-30 17:38:49 +02:00
clairexen
3fb5b4fd8a
Merge pull request #2199 from YosysHQ/mmicko/sim_memory 
sim - error when memrd and memwr detected
 2020-06-30 17:12:51 +02:00
clairexen
275cee71f6
Merge pull request #2201 from YosysHQ/fix_test_cell_ilang 
Use ID macro to fix assertion
 2020-06-30 17:11:13 +02:00
clairexen
79d81b7f4f
Merge pull request #2209 from YosysHQ/verific_update 
Update verific API version check
 2020-06-30 17:05:51 +02:00
Marcelina Kościelnicka
817ae04ee0 simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
Miodrag Milanovic
561890c4e8 Update verific API version check 2020-06-30 12:13:13 +02:00
Alberto Gonzalez
83c595aaac
qbfsat: Add -O[012] options to control pre-solving simplification with ABC. 
Thanks to @mwk for the gate mapping part of the ABC scripts.

Co-Authored-By: Marcelina Kościelnicka <mwk@0x04.net>
 2020-06-30 06:44:17 +00:00
Alberto Gonzalez
f544a2cc84
qbfsat: Fix name-based hole specialization. 
Look for unique connections in the containing module with the $anyconst port Y SigBit on the RHS and use those. If no such connection is found, fall back to using the name of the $anyconst port Y SigBit.
 2020-06-30 01:53:21 +00:00
whitequark
f7fdd99e45
Merge pull request #2205 from whitequark/fix-2204 
techmap: don't drop attributes on replaced cells
 2020-06-30 00:08:08 +00:00
whitequark
a97c13f0ca techmap: don't drop attributes on replaced cells. 
This was introduced in 76c4ee4ea5.

Fixes #2204.
 2020-06-29 23:14:13 +00:00
Zachary Snow
27cec16cda Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
Miodrag Milanović
4160acc0b1
Merge pull request #2200 from YosysHQ/mmicko/fix_expose 
expose pass fix
 2020-06-29 15:16:29 +02:00
Miodrag Milanovic
405b4e97a1 Give error that options are exclusive 2020-06-29 14:45:49 +02:00
Miodrag Milanovic
0545a042f3 cleanup 2020-06-29 14:42:48 +02:00
whitequark
7860fb628f
Merge pull request #2197 from Xiretza/test_cell-shifts 
test_cell: don't generate directional shifts with \B_SIGNED=1
 2020-06-29 12:34:09 +00:00
Miodrag Milanovic
5aae936044 Use ID macro to fix assertion 2020-06-29 13:18:13 +02:00
Miodrag Milanovic
87717d67d1 expose pass fix 2020-06-29 11:56:43 +02:00
Miodrag Milanovic
48b6d3272c sim - error when memrd and memwr detected 2020-06-29 10:33:39 +02:00
Xiretza
e2cfe57edd
test_cell: don't generate directional shifts with \B_SIGNED=1 
This was made an explicit error in e97e33d, "kernel: require \B_SIGNED=0
on $shl, $sshl, $shr, $sshr.".
 2020-06-28 21:30:16 +02:00
Miodrag Milanovic
b822beb1b2 Fix crash in verific frontend 2020-06-26 20:11:01 +02:00
Kamil Rakoczy
76a34dc5f3 Add signed/unsigned tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-26 15:38:20 +02:00
Lukasz Dalek
6f9be939bd Parse macro call attached semicolon as empty expression 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-26 15:38:20 +02:00
Lukasz Dalek
7cb56f34b0 Fix integer signing grammar 
This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:

parameter integer signed i = 0;
parameter integer unsigned i = 0;

Example of incorrect parameters:

parameter signed integer i = 0;
parameter unsigned integer i = 0;

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-26 15:35:56 +02:00
whitequark
3840cfc016
Merge pull request #2193 from whitequark/cxxrtl-help-text 
cxxrtl: update help text
 2020-06-26 08:48:15 +00:00
whitequark
a746c4b605 cxxrtl: update help text. 2020-06-26 08:30:44 +00:00
whitequark
12c016ebdc
Merge pull request #2188 from antmicro/missing-operators 
Add logic-assignments operators
 2020-06-26 07:30:27 +00:00
whitequark
d6bdc09422
Merge pull request #2189 from antmicro/optional-labels 
Add support for optional labels
 2020-06-26 07:29:24 +00:00
clairexen
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs 
Use (and ignore) the expression provided to log_assert in NDEBUG builds
 2020-06-25 18:21:51 +02:00
clairexen
21209d632e
Merge pull request #2135 from boqwxp/qbfsat-timeinfo 
log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver
 2020-06-25 18:18:09 +02:00
clairexen
fb6441731a
Merge pull request #2093 from boqwxp/qbfsat-bugfixes 
qbfsat: Multiple bugfixes
 2020-06-25 18:14:17 +02:00
clairexen
7d795d6fc7
Merge pull request #2192 from YosysHQ/verific_netbus_attr 
verific - import attributes for net buses
 2020-06-25 16:40:30 +02:00
Kamil Rakoczy
39c39848a2 Add sub-assign and and-assign tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 14:32:05 +02:00
Kamil Rakoczy
470df03f3d Move combined assign tests to single file 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 14:19:16 +02:00
Kamil Rakoczy
539087f417 Support missing sub-assign and and-assign operators 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 13:29:06 +02:00
Miodrag Milanovic
4aec50a863 optimization, all items should have same attributes 2020-06-25 09:18:53 +02:00
Kamil Rakoczy
f6d06c9f7b Add xor-assignment test 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 14:46:21 +02:00
Lukasz Dalek
a4b4c22c96 Support missing xor-assign operator 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-06-24 14:32:12 +02:00