Eddie Hung
2b93b8fc74
Merge pull request #1374 from YosysHQ/eddie/fix1371
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Fix two non-deterministic behaviours that cause divergence between compilers
2019-09-15 13:56:07 -07:00
Eddie Hung
9a73adde50
Explicitly order function arguments
2019-09-13 16:18:05 -07:00
Eddie Hung
95e80809a5
Revert "SigSet<Cell*> to use stable compare class"
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This reverts commit 4ea34aaacd
2019-09-13 09:49:15 -07:00
Clifford Wolf
a67d63714b
Fix handling of z_digit "?" and fix optimization of cmp with "z"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-13 13:39:39 +02:00
Eddie Hung
4ea34aaacd
SigSet<Cell*> to use stable compare class
2019-09-12 11:45:02 -07:00
David Shah
6044fff074
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock
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Add equiv_opt -multiclock
2019-09-12 12:26:28 +01:00
Marcin Kościelnicki
f72765090c
Add -match-init option to dff2dffs.
2019-09-11 19:38:20 +02:00
David Shah
c43e52d2d7
Add equiv_opt -multiclock
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Signed-off-by: David Shah <dave@ds0.me>
2019-09-11 13:55:59 +01:00
David Shah
c7f1368cd2
Merge pull request #1362 from xobs/smtbmc-msvc2-build-fixes
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MSVC2 fixes
2019-09-11 09:57:30 +01:00
Eddie Hung
be0eaf3a9a
Fix misspelling
2019-09-09 16:46:33 -07:00
Sean Cross
8d128ba6d0
passes: opt_share: don't statically initialize mergeable_type_map
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In 3d3779b037#1361 ).
Only initialize the map when it's first used, to avoid these static issues.
This fixes #1361 .
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-09 12:40:01 +08:00
Marcin Kościelnicki
a82e8df7d3
techmap: Add support for extracting init values of ports
2019-09-07 16:30:43 +02:00
Eddie Hung
903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival
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Allow arrival times of sequential outputs to be specified to abc9
2019-09-05 12:00:23 -07:00
Clifford Wolf
30f1ac7ce9
Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:51:53 +02:00
Clifford Wolf
694a8f75cf
Add flatten handling of pre-existing wires as created by interfaces, fixes #1145
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:30:58 +02:00
Eddie Hung
ba629e6a28
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-04 15:36:07 -07:00
Eddie Hung
d2306d7b1d
Adopt @cliffordwolf's suggestion
2019-09-03 12:18:50 -07:00
Eddie Hung
d6a84a78a7
Merge remote-tracking branch 'origin/master' into eddie/deferred_top
2019-09-03 10:49:21 -07:00
Eddie Hung
2fa3857963
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-02 12:13:44 -07:00
Eddie Hung
4aa505d1b2
Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc
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ice40_dsp to allow signed multipliers
2019-09-01 10:11:33 -07:00
Miodrag Milanovic
fa5065e9b5
Fix select command error msg, fixes issue #1081
2019-09-01 11:00:09 +02:00
Eddie Hung
17b77fd411
Missing dep for test_pmgen
2019-08-30 14:01:07 -07:00
Eddie Hung
c7f1ccbcb0
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 12:28:35 -07:00
Eddie Hung
999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
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abc9 to not call "clean" at end of run (often called outside)
2019-08-30 12:27:09 -07:00
Eddie Hung
c1459bc748
Do not restrict multiplier to unsigned
2019-08-30 12:22:14 -07:00
Eddie Hung
d2d2816f8c
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-30 10:30:54 -07:00
Eddie Hung
f0fef90e9d
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 10:30:46 -07:00
Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
Eddie Hung
18cabe9370
Output has priority over input when stitching in abc9
2019-08-29 17:24:03 -07:00
Eddie Hung
3e0f73c3df
abc9 to not call "clean" at end of run (often called outside)
2019-08-29 12:12:59 -07:00
Eddie Hung
1467761060
Fix typo that's gone unnoticed for 5 months!?!
2019-08-29 10:33:28 -07:00
Eddie Hung
c4e5310823
Use a dummy box file if none specified
2019-08-28 20:58:55 -07:00
Eddie Hung
116c249601
-auto-top should check $abstract (deferred) modules with (* top *)
2019-08-28 19:59:25 -07:00
Eddie Hung
4eb5847dbd
Cleanup
2019-08-28 18:10:33 -07:00
Eddie Hung
0af64df10c
Account for D port being a constant
2019-08-28 15:32:38 -07:00
Eddie Hung
a45c09c8d1
Account for D port being a constant
2019-08-28 15:31:55 -07:00
Eddie Hung
1b08f861b6
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-28 15:31:48 -07:00
Eddie Hung
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
Eddie Hung
fc727fa5c9
Merge pull request #1334 from YosysHQ/clifford/async2synclatch
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Add $dlatch support to async2sync
2019-08-28 12:36:06 -07:00
Eddie Hung
52c4655de3
No need to replace Q of slice since $shiftx is autoremove-d
2019-08-28 11:06:11 -07:00
Eddie Hung
11e3eb1009
More cleanup
2019-08-28 10:19:35 -07:00
Eddie Hung
86b538bd02
More cleanup
2019-08-28 10:11:09 -07:00
Eddie Hung
c4d1bd988b
Do not use default_params dict, hardcode default values, cleanup
2019-08-28 10:06:40 -07:00
Eddie Hung
c3e9627afe
Always generate if no match
2019-08-28 09:54:56 -07:00
Eddie Hung
0ebe2c9831
Rename test_pmgen arg xilinx_srl.{fixed,variable}
2019-08-28 09:27:03 -07:00
Eddie Hung
ba5d81c7f1
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-28 09:21:03 -07:00
Clifford Wolf
47ffbf554e
Fix typo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:06:42 +02:00
Clifford Wolf
0fda0e821c
Add "paramap" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:03:27 +02:00
Clifford Wolf
c499dc3e73
Add $dlatch support to async2sync
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 09:45:22 +02:00
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init
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In sat: 'x' in init attr should be ignored
2019-08-28 00:18:14 +02:00
