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Add -match-init option to dff2dffs.
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parent
c7f1368cd2
commit
f72765090c
3 changed files with 77 additions and 3 deletions
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@ -34,11 +34,16 @@ struct Dff2dffsPass : public Pass {
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log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n");
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log("dff2dffe for SR over CE priority.\n");
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log("\n");
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log(" -match-init\n");
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log(" Disallow merging synchronous set/reset that has polarity opposite of the\n");
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log(" output wire's init attribute (if any).\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
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bool match_init = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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@ -46,6 +51,10 @@ struct Dff2dffsPass : public Pass {
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// singleton_mode = true;
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// continue;
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// }
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if (args[argidx] == "-match-init") {
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match_init = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -96,9 +105,6 @@ struct Dff2dffsPass : public Pass {
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SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
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SigBit bit_s = sigmap(mux_cell->getPort(ID(S)));
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log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
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log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
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SigBit sr_val, sr_sig;
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bool invert_sr;
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sr_sig = bit_s;
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@ -113,6 +119,23 @@ struct Dff2dffsPass : public Pass {
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invert_sr = false;
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}
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if (match_init) {
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SigBit bit_q = cell->getPort(ID(Q));
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if (bit_q.wire) {
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auto it = bit_q.wire->attributes.find(ID(init));
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if (it != bit_q.wire->attributes.end()) {
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auto init_val = it->second[bit_q.offset];
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if (init_val == State::S1 && sr_val != State::S1)
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continue;
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if (init_val == State::S0 && sr_val != State::S0)
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continue;
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}
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}
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}
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log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
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log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
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if (sr_val == State::S1) {
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if (cell->type == ID($_DFF_N_)) {
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if (invert_sr) cell->type = ID($__DFFS_NN1_);
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