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Author	SHA1	Message	Date
Emil J. Tywoniak	24488a7011	tests: use memory -bram-register in tests/bram	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	2bc6ea7f37	memory: add -bram-register	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	b4b5093a14	memory_bram: add -register	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	1ff7d5acc6	ffmerge: initvals signorm compatibility fixup	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	2dfb691f8b	timinginfo: special-case $specify2 in signorm invariant	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	8ae1d758e2	opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	15fa0b77df	connect: remove input ports on conflict	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	2ed06c4f3b	opt_dff: sigma harder, FfDataSigMapped	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	532d07917d	ff: add FfDataSigMapped	2026-04-16 15:48:58 +02:00
Emil J. Tywoniak	6de3bdc4f4	opt_dff: temporarily disable signorm due to muxtree traversal	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	3df772c59c	tests: fix rtlil roundtrip test	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	2c024d5e74	design: fix signorm commit connectivity to design	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	05fdff65f0	cxxrtl: ignore $input_port	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	00f46cf9ac	flatten: redo signormalization to work around fanout issue	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	ea17cca41f	abstract: fix test signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	319b9e2a4f	signorm: disable passes that use rewrite_sigspecs	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	28d9d206d4	aiger: ignore $input_port	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	0822972e8d	check: stitch info about $connect ports together for driver analysis	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	aa101a0c17	signorm: remove $input cells when leaving	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	03ac80054f	abstract: skip $input_port cells	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	6a5620303e	flatten: skip $input_port cells in template module	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	e2f9a31b8d	signorm: skip const when fixing fanout	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	74610ae0ee	signorm: disable in passes that use swap_names	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	51331a3ffd	opt_expr: fix invert_map	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	9f0e4ff03c	satgen: support $connect	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	1e94e0ba6d	rtlil: add dump_sigmap for hacky signorm debugging	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	43944a6e4b	techmap: disable signorm more	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	3833c4eeac	techmap: disable signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	099d9886a7	opt_hier: disable signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	fa890bdb9e	timinginfo: disable output wire check due to signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	a818fcd36b	rtlil: forbid rewrite_sigspecs in signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	c73f1c9fe9	opt_merge_inc: re add initvals deletion	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	3f0e776036	synth_ice40: always read abc9 model to understand port direction	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	da939d86e5	tests: adjust to input_port and init behavior (sketchy)	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	924dba44c7	tests: adjust to input_port and init behavior (sketchy)	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	be64a31a36	tests: adjust to input_port and init behavior (sketchy)	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	e635affe29	wreduce: fixup initvals after setPort	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	90c3aa0a12	ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	1bb29e6a7e	tests: adjust to input_port and init behavior (sketchy)	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	c7ea35e89b	rtlil: fix zero width SigSpec crash in signorm setPort unsetPort	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	b311a7fc73	bug2920: disable	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	81651178b5	rtlil_bufnorm: fix cell deletion deferral bug	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	e8ebac2823	tests: adjust to input_port and init behavior (sketchy)	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	b756c67aba	check: don't fail on $input_port	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	d46d90ac02	mem: fix signorm cell type morph	2026-04-16 15:48:57 +02:00
Jannis Harder	89589cdbd6	WIP half broken snapshot	2026-04-16 15:48:57 +02:00
Jannis Harder	bc7336499c	WIP remove dead code	2026-04-16 15:48:57 +02:00
nella	413169663d	Merge pull request #5753 from YosysHQ/nella/carry-save-adders ... Add Carry-save adders	2026-04-13 11:16:33 +00:00
nella	4506dffa9f	Fix use after free.	2026-04-13 12:48:05 +02:00
nella	fc71719e6e	Rename csa_tree to arith_tree.	2026-04-13 12:48:05 +02:00