629 commits

Author	SHA1	Message	Date
Akash Levy	4e03e8d877	Add copyright	2024-08-22 18:32:37 -07:00
Akash Levy	34e5bc1129	Merge branch 'YosysHQ:main' into master	2024-08-14 16:56:53 -07:00
Akash Levy	71a7f3fabd	Fix for segfaulting	2024-08-14 16:00:03 -07:00
Akash Levy	8118380726	Update to fix infinite loop	2024-08-14 13:40:30 -07:00
Akash Levy	83dfdd9dd5	Fix splitfanout	2024-08-14 13:19:58 -07:00
Akash Levy	63a421aed8	Small comment update	2024-08-14 05:37:28 -07:00
Akash Levy	2deabdd640	Make splitfanout more robust	2024-08-14 05:29:03 -07:00
Akash Levy	5777bed8ed	Add splitfanout first pass	2024-08-14 03:24:24 -07:00
Martin Povišer	3057c13a66	Improve libparse encapsulation	2024-08-13 18:47:36 +02:00
Akash Levy	953f405a84	Merge branch 'YosysHQ:main' into master	2024-08-07 11:47:52 -07:00
Martin Povišer	4c3203866f	exec: Add missing newline	2024-08-07 13:02:00 +02:00
Akash Levy	bafce0ddee	Revert SCC	2024-07-30 23:08:06 -07:00
Akash Levy	c0af4604bc	Update Yosys	2024-07-30 16:55:18 -07:00
Emil J. Tywoniak	4b29f64142	cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter	2024-07-29 10:26:02 +02:00
Akash Levy	983d404e93	Smallfix	2024-06-17 20:04:38 -07:00
Akash Levy	c8dff00ca6	Smallfix	2024-06-17 16:07:26 -07:00
Akash Levy	719bbd7523	Improve SCC reporting	2024-06-17 14:18:41 -07:00
Akash Levy	e23e33441f	Update yosys from upstream	2024-06-15 14:23:24 -07:00
Miodrag Milanovic	9b82a44d25	Fix help message typo	2024-06-07 08:26:59 +02:00
Akash Levy	e0d96d35a1	Merge branch 'YosysHQ:main' into master	2024-06-01 23:47:26 -07:00
Martin Povišer	4b67f3757f	Merge pull request #4404 from YosysHQ/povik/bbox_derive ... box_derive: New command to derive modules for boxes	2024-05-31 19:09:18 +02:00
Martin Povišer	b230c95cc4	select: Adjust help	2024-05-29 20:41:56 +02:00
Akash Levy	5173e329ea	Sync yosys	2024-05-21 19:07:13 -07:00
Martin Povišer	49906be776	select: Introduce -assert-mod-count	2024-05-21 16:34:38 +02:00
Martin Povišer	adc1a01490	select: Refactor some flag validation	2024-05-21 16:29:20 +02:00
Martin Povišer	c0a196173a	Rename bbox_derive to box_derive	2024-05-21 16:18:03 +02:00
Martin Povišer	5c929a91c2	bbox_derive: Write help	2024-05-21 14:57:37 +02:00
Martin Povišer	88af059fad	bbox_derive: Fix done base type confusion	2024-05-21 14:57:26 +02:00
Akash Levy	261bc561fa	Allow for gzip magic in stat	2024-05-05 04:21:47 -07:00
Emil J. Tywoniak	44b0fdc2bf	bbox_derive: add assert and debug print	2024-05-03 20:43:01 +02:00
Emil J. Tywoniak	e8c58a5528	bbox_derive: fix unininitialized memory UB when run with no named args	2024-05-03 20:41:42 +02:00
Martin Povišer	4c000d3aba	Add new bbox_derive command for blackbox derivation	2024-05-03 20:39:11 +02:00
Martin Povišer	b00abe4a26	Extend log command with -push, -pop, -header options	2024-04-10 11:49:20 +02:00
Martin Povišer	47931f9050	Merge pull request #4295 from gadfort/add-ports-stat ... add port statistics to stat command	2024-04-08 11:12:02 +02:00
Peter Gadfort	160e3e089a	add port statistics to stat command	2024-03-22 09:20:20 -04:00
Martin Povišer	206d894c56	check: Omit private wires in loop report	2024-03-11 10:45:36 +01:00
Martin Povišer	d01728aaa5	celledges: Register async FF paths	2024-03-11 10:45:36 +01:00
Martin Povišer	4fdcf388d3	check: Assert edges data is not out-of-bounds	2024-03-11 10:45:17 +01:00
Martin Povišer	b6112b3551	check: Consider read ports in loop detection	2024-03-11 10:45:17 +01:00
Martin Povišer	fa74d0bd1a	check: Use cell edges data in detecting combinational loops	2024-03-11 10:43:49 +01:00
Martin Povišer	c5ae74af34	check: Improve found loop logging ... Print the detected loop in-order, and include source location for each node, if available.	2024-03-11 10:43:49 +01:00
Jannis Harder	d8cdc213a6	rename -witness: Bug fix and rename formal cells ... Rename formal cells in addition to witness signals. This is required to reliably track individual property states for the non-smtbmc flows. Also removes a misplced `break` which resulted in only partial witness renaming.	2024-03-04 16:53:03 +01:00
Miodrag Milanović	a3c81f4d62	Merge pull request #4216 from YosysHQ/show_href ... show: Add option to add cell/wire "src" attribute into graphviz attribute href	2024-02-19 20:50:53 +01:00
N. Engelhardt	4b99db0b73	Merge pull request #4177 from povik/connect-extra_args ... connect: Do interpret selection arguments	2024-02-19 15:18:37 +01:00
Ethan Mahintorabi	b8a1009de9	Update passes/cmds/stat.cc ... Make reporting line more clear about the non cumulative area of sequential cells Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>	2024-02-16 07:44:09 -08:00
Ethan Mahintorabi	f0df0e3912	update type and variable names ... Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-16 00:01:44 +00:00
Ethan Mahintorabi	2d8343d423	update type and variable names ... Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-15 23:59:19 +00:00
Miodrag Milanovic	834276a2f7	show: Add option to add cell/wire "src" attribute into graphviz attribute href	2024-02-14 09:50:53 +01:00
Ethan Mahintorabi	8566489d85	stat: Add sequential area output to stat -liberty ... Checks to see if a cell is of type ff in the liberty, and keeps track of an additional area value. ``` Chip area for module '\addr': 92.280720 Sequential area for module '\addr': 38.814720 ``` Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2024-02-09 23:51:00 +00:00
Claire Xen	1b73b5beb7	Merge pull request #4174 from YosysHQ/claire/overwrite ... Add API to overwrite existing pass from plugin	2024-02-05 23:49:24 +01:00