Krystine Sherwin
23f9bc6ffd
analogdevices: Fixup SP2_1024x18_BP
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Was incorrectly _FP, and SDP_1024x18_FP for T40LP was missing.
2025-11-10 17:24:46 +13:00
Krystine Sherwin
eb2b57b084
analogdevices: Use dump_meminit
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Add `INIT_FILE` and `SIM_INIT_BEHAVIOR` parameters.
Add `init any` to non-full ADI ram blocks.
2025-11-10 17:23:41 +13:00
Krystine Sherwin
7f8334e781
WIP dump_meminit
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Developed for synth_analogdevices, but there's no reason it couldn't be used for others.
2025-11-10 16:58:06 +13:00
Lofty
1ceb5b2930
analogdevices: double LUT RAM cost
2025-11-09 15:44:35 +00:00
Lofty
22e04ac81e
analogdevices: ignore $assert cells
2025-11-09 15:44:35 +00:00
Krystine Sherwin
09b5f610f7
analogdevices: Extra tests
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`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
2025-11-09 15:44:35 +00:00
Krystine Sherwin
fc2e468fd9
analogdevices: Fixing up bram
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Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
2025-11-09 15:44:35 +00:00
Krystine Sherwin
2ab84648b4
analogdevices: Add BRAM options
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Enable `-force-params`, and tidy up lutram mapping too.
2025-11-09 15:44:35 +00:00
Krystine Sherwin
e232f92afb
memory_libmap: Add -force-params
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Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
2025-11-09 15:44:35 +00:00
Lofty
f8fc7bfd3d
analogdevices: LUT RAM only on positive edge
2025-11-09 15:44:35 +00:00
Lofty
8101eca236
analogdevices: DSP tweaks
2025-11-09 15:44:35 +00:00
Lofty
0261d18759
analogdevices: DSP inference
2025-11-09 15:44:35 +00:00
Lofty
d62d789ce4
analogdevices: remove cells_xtra
2025-11-09 15:44:35 +00:00
Lofty
dd5fbebe8e
analogdevices: timings for t40lp
2025-11-09 15:44:35 +00:00
Lofty
47c5a52674
analogdevices: use single tech param
2025-11-09 15:44:35 +00:00
Lofty
4aa5008c56
analogdevices: expreso does not care about clock buffers
2025-11-09 15:44:35 +00:00
Lofty
3e1ca2f3e6
analogdevices: prepare for t40lp timings
2025-11-09 15:44:35 +00:00
Krystine Sherwin
dc76af06a0
analogdevices: Adding RBRAM2 and -tech
2025-11-09 15:44:34 +00:00
Krystine Sherwin
3f90865a28
analogdevices: (some) Native BRAM
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Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
2025-11-09 15:44:34 +00:00
Krystine Sherwin
b3f0d13c26
analogdevices: Update lutram.ys test
2025-11-09 15:44:34 +00:00
Krystine Sherwin
d5074c5849
analogdevices: Native LUTRAM primitives
2025-11-09 15:44:34 +00:00
Lofty
a2983851f0
analogdevices: LUTRAM config
2025-11-09 15:44:34 +00:00
Lofty
2b384b8d53
analogdevices: update timing model
2025-11-09 15:44:34 +00:00
Lofty
75fc08e876
I thought I removed this...
2025-11-09 15:44:34 +00:00
Lofty
af57ebafa0
analogdevices: user retargeting
2025-11-09 15:44:34 +00:00
Lofty
a5271bc482
analogdevices: more housekeeping
2025-11-09 15:44:34 +00:00
Lofty
5abb8fd6f1
analogdevices: remove some extra cells!
2025-11-09 15:44:34 +00:00
Lofty
9f26034176
test suite
2025-11-09 15:44:34 +00:00
Lofty
a1d13843ad
synth_analogdevices: remove scopeinfo cells
2025-11-09 15:44:34 +00:00
Lofty
f4c003b1c5
Create synth_analogdevices
2025-11-09 15:44:34 +00:00
github-actions[bot]
5d0847f6fb
Bump version
2025-11-07 00:24:35 +00:00
KrystalDelusion
24b69cabaa
Merge pull request #5422 from YosysHQ/krys/SVI_support
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Catch partial support of SVI
2025-11-07 11:16:07 +13:00
Miodrag Milanović
691d6b8508
Merge pull request #5469 from YosysHQ/update_abc
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Update ABC
2025-11-06 21:19:39 +01:00
Emil J
a16fc9b4f3
Merge pull request #5467 from YosysHQ/emil/liberty-unquoted-expressions
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libparse: support unquoted expressions
2025-11-06 19:45:17 +01:00
Emil J
3a23d4458e
Merge pull request #5470 from YosysHQ/emil/unit-test-makefile
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Makefile: clean unit test on clean, ensure prepared to fix parallelism
2025-11-06 19:05:57 +01:00
Miodrag Milanovic
dc9a787025
Fix out of tree clean
2025-11-06 14:28:28 +01:00
Emil J. Tywoniak
2bf7aac9d1
Makefile: clean unit test on clean, ensure prepared to fix parallelism
2025-11-06 13:59:14 +01:00
Emil J. Tywoniak
fdcc4c1507
libparse: remove leftover comments
2025-11-06 13:30:09 +01:00
Emil J
a2aeef6c96
Merge pull request #5461 from rocallahan/reset-abc-config
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Fix regression in configuring ABC techmapping
2025-11-06 11:58:04 +01:00
Miodrag Milanovic
75ce33c7b2
Update ABC
2025-11-06 09:54:47 +01:00
github-actions[bot]
3d5b1e0a93
Bump version
2025-11-06 00:24:21 +00:00
Miodrag Milanović
5b2252ffd8
Merge pull request #5468 from YosysHQ/pyosys_outof
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Fix generatory.py location for out of tree builds
2025-11-05 18:13:14 +01:00
Robert O'Callahan
0f770285f3
Move global ABC configuration variables into AbcConfig and initialize them properly
2025-11-05 13:56:04 +00:00
Martin Povišer
45bb5c690d
Merge pull request #5460 from povik/timeest-comb
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timeest: Add top ports launching/sampling
2025-11-05 14:29:34 +01:00
Miodrag Milanovic
f8341affe3
Fix generatory.py location for out of tree builds
2025-11-05 14:20:30 +01:00
Emil J. Tywoniak
90553267b0
libparse: fix quoting and negedge in filterlib -verilogsim
2025-11-05 14:13:58 +01:00
Emil J. Tywoniak
504b668ea6
libparse: fix verilogsim negedge
2025-11-05 13:49:05 +01:00
Emil J. Tywoniak
b0a3d6a3e7
libparse: fix up tests since liberty expression parsing now normalizes the form of these expressions
2025-11-05 13:06:12 +01:00
Emil J. Tywoniak
bf29f6dc11
libparse: tolerate closing quotes in expression parsing
2025-11-05 13:06:09 +01:00
Emil J. Tywoniak
4fac7a1b20
libparse: fix space before closing paren in expressions
2025-11-05 13:05:56 +01:00
