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libparse: fix up tests since liberty expression parsing now normalizes the form of these expressions

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This commit is contained in:
Emil J. Tywoniak 2025-11-05 13:05:30 +01:00
parent bf29f6dc11
commit b0a3d6a3e7
8 changed files with 176 additions and 17 deletions
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2
tests/liberty/XNOR2X1.lib.verilogsim.ok
View file

@ -2,5 +2,5 @@ module XNOR2X1 (B, A, Y);
input B;
input A;
output Y;
assign Y = !(B&!A|!B&A); // "!(B&!A|!B&A)"
assign Y = (~((B&(~A))|((~B)&A))); // "!(B&!A|!B&A)"
endmodule

4
tests/liberty/dff.lib
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@ -5,7 +5,7 @@ library(dff) {
area : 1;
ff("IQ", "IQN") {
next_state : "(D)";
clocked_on : "CLK";
clocked_on : (CLK);
}
pin(D) {
direction : input;
@ -15,7 +15,7 @@ library(dff) {
}
pin(Q) {
direction: output;
function : "IQ";
function : IQ;
}
}

4
tests/liberty/dff.lib.filtered.ok
View file

@ -3,7 +3,7 @@ library(dff) {
area : 1 ;
ff("IQ", "IQN") {
next_state : "(D)" ;
clocked_on : "CLK" ;
clocked_on : ( CLK ) ;
}
pin(D) {
direction : input ;
@ -13,7 +13,7 @@ library(dff) {
}
pin(Q) {
direction : output ;
function : "IQ" ;
function : IQ ;
}
}
}

6
tests/liberty/dff.lib.verilogsim.ok
View file

@ -3,10 +3,10 @@ module dff (D, CLK, Q);
input D;
input CLK;
output Q;
assign Q = IQ; // "IQ"
assign Q = IQ; // IQ
always @(posedge CLK) begin
// "(D)"
"IQ" <= (D);
"IQN" <= ~((D));
"IQ" <= D;
"IQN" <= ~(D);
end
endmodule

18
tests/liberty/normal.lib.verilogsim.ok
View file

@ -1,13 +1,13 @@
module inv (A, Y);
input A;
output Y;
assign Y = ~A; // "A'"
assign Y = (~A); // "A'"
endmodule
module tri_inv (A, S, Z);
input A;
input S;
output Z;
assign Z = ~A; // "A'"
assign Z = (~A); // "A'"
endmodule
module buffer (A, Y);
input A;
@ -18,26 +18,26 @@ module nand2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A&B); // "(A * B)'"
assign Y = (~(A&B)); // "(A * B)'"
endmodule
module nor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A|B); // "(A + B)'"
assign Y = (~(A|B)); // "(A + B)'"
endmodule
module xor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = (A&~B)|(~A&B); // "(A *B') + (A' * B)"
assign Y = ((A&(~B))|((~A)&B)); // "(A *B') + (A' * B)"
endmodule
module imux2 (A, B, S, Y);
input A;
input B;
input S;
output Y;
assign Y = ~(&(A&S)|(B&~S)&); // "( (A * S) + (B * S') )'"
assign Y = (~((A&S)|(B&(~S)))); // "( (A * S) + (B * S') )'"
endmodule
module dff (D, CLK, RESET, PRESET, Q, QN);
reg "IQ", "IQN";
@ -89,14 +89,14 @@ module aoi211 (A, B, C, Y);
input B;
input C;
output Y;
assign Y = ~((A&B)|C); // "((A * B) + C)'"
assign Y = (~((A&B)|C)); // "((A * B) + C)'"
endmodule
module oai211 (A, B, C, Y);
input A;
input B;
input C;
output Y;
assign Y = ~((A|B)&C); // "((A + B) * C)'"
assign Y = (~((A|B)&C)); // "((A + B) * C)'"
endmodule
module halfadder (A, B, C, Y);
input A;
@ -104,7 +104,7 @@ module halfadder (A, B, C, Y);
output C;
assign C = (A&B); // "(A * B)"
output Y;
assign Y = (A&~B)|(~A&B); // "(A *B') + (A' * B)"
assign Y = ((A&(~B))|((~A)&B)); // "(A *B') + (A' * B)"
endmodule
module fulladder (A, B, CI, CO, Y);
input A;

60
tests/liberty/unquoted.lib Normal file
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@ -0,0 +1,60 @@
library(dff_unquoted) {
cell (dff1) {
area : 1;
ff("IQ", "IQN") {
next_state : !D;
clocked_on : (CLK);
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(Q) {
direction: output;
function : IQ;
}
}
cell (dff2) {
area : 1;
ff(IQ, IQN) {
next_state : D';
clocked_on : CLK;
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
}
cell (dffe) {
area : 6;
ff("IQ", "IQN") {
next_state : (D&EN) | (IQ&!EN);
clocked_on : !CLK;
}
pin(D) {
direction : input;
}
pin(EN) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
}

60
tests/liberty/unquoted.lib.filtered.ok Normal file
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@ -0,0 +1,60 @@
library(dff_unquoted) {
cell(dff1) {
area : 1 ;
ff("IQ", "IQN") {
next_state : !D ;
clocked_on : ( CLK ) ;
}
pin(D) {
direction : input ;
}
pin(CLK) {
direction : input ;
}
pin(Q) {
direction : output ;
function : IQ ;
}
}
cell(dff2) {
area : 1 ;
ff(IQ, IQN) {
next_state : D ' ;
clocked_on : CLK ;
}
pin(D) {
direction : input ;
}
pin(CLK) {
direction : input ;
}
pin(Q) {
direction : output ;
function : "IQ" ;
}
}
cell(dffe) {
area : 6 ;
ff("IQ", "IQN") {
next_state : ( D & EN ) | ( IQ & ! EN ) ;
clocked_on : !CLK ;
}
pin(D) {
direction : input ;
}
pin(EN) {
direction : input ;
}
pin(CLK) {
direction : input ;
}
pin(Q) {
direction : output ;
function : "IQ" ;
}
pin(QN) {
direction : output ;
function : "IQN" ;
}
}
}

39
tests/liberty/unquoted.lib.verilogsim.ok Normal file
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@ -0,0 +1,39 @@
module dff1 (D, CLK, Q);
reg "IQ", "IQN";
input D;
input CLK;
output Q;
assign Q = IQ; // IQ
always @(posedge CLK) begin
// !D
"IQ" <= (~D);
"IQN" <= ~((~D));
end
endmodule
module dff2 (D, CLK, Q);
reg IQ, IQN;
input D;
input CLK;
output Q;
assign Q = IQ; // "IQ"
always @(posedge CLK) begin
// D '
IQ <= (~D);
IQN <= ~((~D));
end
endmodule
module dffe (D, EN, CLK, Q, QN);
reg "IQ", "IQN";
input D;
input EN;
input CLK;
output Q;
assign Q = IQ; // "IQ"
output QN;
assign QN = IQN; // "IQN"
always @(posedge (~CLK)) begin
// ( D & EN ) | ( IQ & ! EN )
"IQ" <= ((D&EN)|(IQ&(~EN)));
"IQN" <= ~(((D&EN)|(IQ&(~EN))));
end
endmodule