Miodrag Milanovic
60f126cd00
Release version 0.55
2025-07-07 11:26:04 +02:00
Emil J
468cbb800c
Merge pull request #5206 from yrabbit/cell-creation-script-5a
...
Gowin. BUGFIX. Fix multi-line descriptions.
2025-07-07 10:36:42 +02:00
N. Engelhardt
642756a9c6
Merge pull request #5178 from jix/sva_cover_only_followed_by
2025-07-07 10:07:06 +02:00
Martin Povišer
62067cd6cb
Update docs after addition of new pass
2025-07-05 16:45:52 +02:00
Martin Povišer
22a44e4333
Start opt_hier
2025-07-05 16:45:52 +02:00
github-actions[bot]
99f7d79abb
Bump version
2025-07-05 00:23:55 +00:00
Miodrag Milanović
afd0ba0099
Merge pull request #5208 from YosysHQ/micko/replace_const_exprs
...
verific: enable replacing const exprs in static elaboration by default
2025-07-04 10:35:03 +02:00
Gary Wong
5feb1a1752
verilog: add support for SystemVerilog string literals.
...
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
Miodrag Milanovic
eed3bc243f
verific: enable replacing const exprs in static elaboration by default
2025-07-02 11:54:19 +02:00
YRabbit
85e7c68fc6
Gowin. BUGFIX. Fix multi-line descriptions.
...
If let's say the enumeration of inputs took several lines, then all
after the first one were ignored. Since the first line ended with a
comma, an error was generated when trying to use the resulting file.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-07-02 12:39:18 +10:00
N. Engelhardt
8a4f465143
update test to use suggested selection for assertions
2025-07-01 11:46:27 +02:00
N. Engelhardt
7b0c1fe491
Merge pull request #5102 from YosysHQ/krys/verilog_no_select
2025-06-30 13:35:17 +00:00
Miodrag Milanović
54013c6da7
Merge pull request #5162 from YosysHQ/micko/attrmap
...
Make attrmap able to alter memory attributes as well
2025-06-30 15:24:04 +02:00
github-actions[bot]
67583fee48
Bump version
2025-06-30 00:27:10 +00:00
KrystalDelusion
74575691a0
Merge pull request #5180 from YosysHQ/krys/test_asan
...
Add ASAN to CI
2025-06-30 10:40:34 +12:00
Krystine Sherwin
017524d7a2
tests/verific: Don't ASAN verific
2025-06-28 11:33:18 +12:00
Krystine Sherwin
e6961d8c9f
CI: Test with ASAN as well
...
New matrix variable for sanitizer, running `undefined` and `address` separately
(because they are mutually exclusive). Probably don't need to run both
sanitizers on both os targets, but it's probably fine.
2025-06-28 11:33:18 +12:00
N. Engelhardt
ef3f541501
add linecoverage command to generate lcov report from selection
2025-06-26 13:21:53 +02:00
Emil J. Tywoniak
2b659626a3
rename: add -unescape
2025-06-24 12:33:33 +02:00
Emil J
513f0f16dd
Merge pull request #5173 from RonxBulld/refine_setup_shutdown_flags
...
Allows calling yosys_shutdown and then yosys_setup to restart.
2025-06-24 12:32:52 +02:00
Emil J. Tywoniak
73cbcffbbb
fixup! dfflibmap: propagate negated next_state to output correctly
2025-06-24 12:31:30 +02:00
Emil J. Tywoniak
778079b058
dfflibmap: propagate negated next_state to output correctly
2025-06-24 12:01:12 +02:00
github-actions[bot]
a0a77cd1d0
Bump version
2025-06-24 00:24:55 +00:00
Gary Wong
34a2abeddb
verilog: fix parser "if" memory errors.
...
Fix buggy memory allocation introduced in #5152 :
1) clean up ast_stack to reflect AST node rearrangement when necessary,
to avoid dangling pointer;
2) call free_attr() on unused attribute list when no new syntax node is
created, to avoid leaking it.
2025-06-22 23:57:42 -04:00
George Rennie
170933ecb0
Merge pull request #5165 from georgerennie/george/opt_dff_uaf
...
opt_dff: don't remove cells until all have been visited to prevent UAF
2025-06-20 23:33:26 +01:00
Krystine Sherwin
beaca05b40
Include boxes in attrmap
...
Rename `selected_members` iterator to memb.
Add comment on `selected_processes` loop for clarity.
2025-06-21 09:49:56 +12:00
github-actions[bot]
44aa313ba9
Bump version
2025-06-20 00:24:40 +00:00
garytwong
834a7294b7
verilog: fix string literal regular expression ( #5187 )
...
* verilog: fix string literal regular expression.
A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.
* verilog: add regression test for string literal regex bug.
Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af40aa7eaf
2025-06-19 12:41:18 -04:00
Emil J. Tywoniak
4276756f32
fixup! const2ast: add diagnostics tests
2025-06-16 22:50:31 +02:00
Emil J. Tywoniak
49cd3887a7
const2ast: add diagnostics tests
2025-06-16 21:48:12 +02:00
Emil J. Tywoniak
41107e5473
log: add -expect types prefix-log, prefix-warning, prefix-error
2025-06-16 21:26:08 +02:00
github-actions[bot]
cd71f190cd
Bump version
2025-06-14 00:24:06 +00:00
Krystine Sherwin
fa68299b25
tests/verific: Add chformal tests
2025-06-14 11:06:38 +12:00
Krystine Sherwin
45131f4425
chformal: Add -assert2cover option
...
Also add to chformal tests.
2025-06-14 10:54:23 +12:00
KrystalDelusion
efa30dfdf8
Merge pull request #5176 from YosysHQ/krys/no_cxxopt_split
...
driver.cc: Don't split options on commas
2025-06-14 10:39:28 +12:00
Jannis Harder
f019e44e74
verificsva: Support the followed-by operator in cover mode
...
The implementation for the implication operator in cover mode actually
implements the followed-by operator, so we can re-use it unchanged.
It is not always the correct behavior for the implication operator in
cover mode, but a) it will only cause false positives not miss anything
so if the behavior is unexpected it will be visible in the produced
traces, b) it is unlikely to make a difference for most properties one
would practically use in cover mode, c) at least one other widely used
SVA implementations behaves the same way and d) it's not clear whether
we can fix this without rewriting most of verificsva.cc
2025-06-13 21:27:31 +02:00
KrystalDelusion
4ade617c41
driver.cc: Don't split options on commas
2025-06-13 10:31:53 +12:00
KrystalDelusion
67f8de54dc
Merge pull request #5160 from garytwong/fast-lex
...
verilog: improve string literal matching speed (fixes #5076 )
2025-06-13 09:57:01 +12:00
KrystalDelusion
82888580ac
Merge pull request #5152 from garytwong/unique-if
...
verilog: implement SystemVerilog unique/unique0/priority if semantics.
2025-06-13 09:56:53 +12:00
Emil J
c0f52c6ead
Merge pull request #5167 from YosysHQ/emil/fix-splitnets-single-bit-vector
...
splitnets: handle single-bit vectors consistently
2025-06-11 22:47:48 +02:00
Miodrag Milanović
e0747b71b7
Merge pull request #5174 from YosysHQ/micko/windows_action
...
Update CI, windows-2019 is deprecated
2025-06-10 08:06:38 +02:00
github-actions[bot]
c561ba84e3
Bump version
2025-06-10 00:24:41 +00:00
Miodrag Milanovic
a5edbc8836
Update CI, windows-2019 is deprecated
2025-06-09 19:07:53 +02:00
Miodrag Milanovic
c16cc539d4
Next dev cycle
2025-06-09 08:12:26 +02:00
Miodrag Milanovic
db72ec3bde
Release version 0.54
2025-06-09 07:23:54 +02:00
N. Engelhardt
0b19f628e9
Merge pull request #5172 from YosysHQ/nak/reduce_warning_spam
2025-06-08 06:50:56 +00:00
N. Engelhardt
cb79e28046
Merge pull request #5159 from YosysHQ/krys/fixing_selections
2025-06-08 06:40:15 +00:00
RonxBulld
d079240d38
Allows calling yosys_shutdown and then yosys_setup to restart.
2025-06-07 22:21:09 +08:00
github-actions[bot]
2a25d92413
Bump version
2025-06-07 00:24:11 +00:00
George Rennie
7160c91800
tests: add test for #5164 opt_dff -sat UAF
2025-06-06 23:46:23 +01:00
