Lofty
8cc9aa7fc6
intel_alm: drop quartus support
2024-05-03 11:32:33 +01:00
Miodrag Milanovic
0c7ac36dcf
Add workflows and CODEOWNERS and fixed gitignore
2024-04-11 14:56:00 +02:00
Miodrag Milanovic
4ac10040ce
Enable SV for localparam use by Efinix cell_sim
2024-04-08 12:45:43 +02:00
Jannis Harder
331ac5285f
tests: Run async2sync before sat and/or sim to handle $check cells
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Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.
While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.
2024-02-01 16:14:11 +01:00
N. Engelhardt
d87bd7ca3f
Merge pull request #3887 from kivikakk/env-bash
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tests: use /usr/bin/env for bash.
2023-12-18 16:33:35 +01:00
Martin Povišer
22cc4aff51
quicklogic: Test TDP36K inference with initial data
2023-12-04 15:52:03 +01:00
Krystine Sherwin
e5c32f399a
synth_quicklogic: Testing double_sync_ram_tdp
2023-12-04 15:52:03 +01:00
Krystine Sherwin
97354782c0
Adding double_sync_ram_tdp to blockram.v
2023-12-04 15:52:03 +01:00
Krystine Sherwin
215a777eb3
qlf_tests: minor adjustment
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Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
2023-12-04 15:52:03 +01:00
N. Engelhardt
33ca6994b7
remove example test
2023-12-04 15:52:03 +01:00
N. Engelhardt
3c5b0ab164
fix test setup for synth_quicklogic memory tests
2023-12-04 15:52:03 +01:00
Krystine Sherwin
509d176523
attempting to sim split memory tests
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and failing
2023-12-04 15:52:03 +01:00
Krystine Sherwin
0d1668c1ee
QLF_TDP36K: asymmetric simulation tests
2023-12-04 15:52:03 +01:00
Krystine Sherwin
497cd021af
QLF_TDP36K: truncation tests matter
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Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
7f12d0ba95
QLF_TDP36K: more basic tdp/sdp sim tests
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Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
2023-12-04 15:52:03 +01:00
Krystine Sherwin
3d08ed216d
QLF_TDP36K: parameterised sim test gen
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Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ba3be3fd1c
QLF_TDP36K: test bram_tdp post synth
2023-12-04 15:52:03 +01:00
N. Engelhardt
f9c8978128
add example memory test
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ede4eaeee2
quicklogic: wildcard asymmetric memory tests
2023-12-04 15:52:03 +01:00
Krystine Sherwin
8ded7020f4
tests: asymmetric sync rams now correctly asymmetric
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Also both use the same named parameters for better mirroring.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ba09866217
quicklogic: testing port widths on split rams
2023-12-04 15:52:03 +01:00
Krystine Sherwin
1a843b2a86
quicklogic: testing 1:4 assymetric memory
2023-12-04 15:52:03 +01:00
Krystine Sherwin
7513bfcbfe
quicklogic: fix double width read
2023-12-04 15:52:03 +01:00
Krystine Sherwin
8d3b238b9b
quicklogic: Testing split TDP36K
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Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
991850e1c9
quicklogic: Initial blockram tests
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Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
2023-12-04 15:52:03 +01:00
Martin Povišer
a5c8d246f7
quicklogic: Add k6n10f DSP test
2023-12-04 15:52:03 +01:00
Martin Povišer
db9e5b4f14
quicklogic: Fix dffs.ys test
2023-12-04 15:52:03 +01:00
Martin Povišer
554d8caef7
quicklogic: Add basic k6n10f tests
2023-12-04 15:52:03 +01:00
Martin Povišer
6672b6c1b3
quicklogic: Move pp3 tests one level down
2023-12-04 15:52:02 +01:00
N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
Lofty
7ae4041e20
ice40, ecp5, gowin: enable ABC9 by default
2023-11-13 15:28:13 +00:00
Lofty
b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default"
2023-11-03 14:52:52 +00:00
Lofty
32082477b5
ice40, ecp5: enable ABC9 by default
2023-11-03 08:52:54 +00:00
Martin Povišer
62d6338688
quicklogic: Fix pp3 dffs test
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Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
2023-10-12 12:45:40 +02:00
Miodrag Milanovic
a42c630264
put back previous test state, due to default change
2023-08-29 10:21:58 +02:00
Miodrag Milanovic
3b9ebfa672
Addressed code review comments
2023-08-25 11:10:20 +02:00
Miodrag Milanovic
ea50d96135
fixed tests
2023-08-23 10:54:29 +02:00
Charlotte
d130f7fca2
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
Miodrag Milanovic
e6f7cf3b29
Update tests
2023-06-09 14:41:45 +02:00
Eddie Hung
862631d657
Add ABC9 DSP cascade test
2023-05-25 18:42:08 +01:00
Lofty
00b0e850db
intel_alm: re-enable carry chains for ABC9
2023-05-25 18:28:10 +01:00
Ralf Fuest
30f1d10948
gowin: Fix X output of $alu techmap
2023-05-01 17:56:41 +02:00
Benjamin Barzen
8611429237
ABC9: Cell Port Bug Patch ( #3670 )
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* ABC9: RAMB36E1 Bug Patch
* Add simplified testcase
* Also fix xaiger writer for under-width output ports
* Remove old testcase
* Missing top-level input port
* Fix tabs
---------
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2023-04-22 16:24:36 -07:00
Miodrag Milanovic
0f5e7c244d
add additional dff and lutram tests
2023-04-06 09:10:14 +02:00
Miodrag Milanovic
54d313efc3
add test for CCU2D
2023-04-06 09:10:14 +02:00
Miodrag Milanovic
61da330a38
Update tests
2023-03-20 09:58:41 +01:00
gatecat
2ab3747cc9
fabulous: Add support for mapping carry chains
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-27 09:50:34 +01:00
KrystalDelusion
f80920bd9f
Genericising bug1836.ys
2023-02-21 05:23:16 +13:00
KrystalDelusion
445a801a85
bug3205.ys removed
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Made redundant by TDP test(s) in memories.ys
2023-02-21 05:23:16 +13:00
KrystalDelusion
51c2d476c2
Removing extra default_nettype lines
2023-02-21 05:23:16 +13:00
