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yosys/tests/arch
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Krystine Sherwin 8d3b238b9b quicklogic: Testing split TDP36K 
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
2023-12-04 15:52:03 +01:00
..
anlogic Update tests 2023-06-09 14:41:45 +02:00
common quicklogic: Testing split TDP36K 2023-12-04 15:52:03 +01:00
ecp5 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
efinix efinix: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
fabulous fabulous: Add support for mapping carry chains 2023-02-27 09:50:34 +01:00
gatemate Update tests 2023-06-09 14:41:45 +02:00
gowin ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
ice40 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
intel_alm Update tests 2023-06-09 14:41:45 +02:00
machxo2 put back previous test state, due to default change 2023-08-29 10:21:58 +02:00
nexus Update tests 2023-06-09 14:41:45 +02:00
quicklogic quicklogic: Testing split TDP36K 2023-12-04 15:52:03 +01:00
xilinx Update tests 2023-06-09 14:41:45 +02:00
run-test.sh Add default assignments to SB_LUT4 2021-04-20 12:46:21 +02:00