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185 commits

Author SHA1 Message Date
Marcelina Kościelnicka 18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg. 
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
 2021-05-25 22:42:03 +02:00
Marcelina Kościelnicka 96c7d60304 memory_bram: Respect write port priority. 2021-05-25 16:28:33 +02:00
Marcelina Kościelnicka e0736c1622 Add memory_narrow pass. 2021-05-25 03:04:13 +02:00
Marcelina Kościelnicka 47f958ce45 memory_share: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka c1a4730739 memory_map: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka 69bf5c81c7 Reject wide ports in some passes that will never support them. 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka df2b79ca76 memory_share: Use Mem helpers. 2021-05-23 23:16:12 +02:00
Marcelina Kościelnicka afd5366fc2 extract_rdff: Add initvals parameter. 
This is not used yet, but will be needed when read port reset/initial
value support lands.
 2021-05-23 22:05:26 +02:00
Marcelina Kościelnicka d905990d01 memory_share: Split off feedback path finding as a separate pass. 
memory_share is actually three passes in a trenchcoat.  Split off the
one that has the least in common with the other two as a separate pass.
 2021-05-23 18:30:39 +02:00
Marcelina Kościelnicka 1eea06bcc0 Add new helper class for merging FFs into cells, use for memory_dff. 
Fixes #1854.
 2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka 039f4f48d5 memory_memx: Use Mem helper. 2021-05-22 22:31:07 +02:00
Marcelina Kościelnicka 8c734e07b8 memory_dff: Use Mem helper. 2021-05-21 02:26:27 +02:00
Marcelina Kościelnicka a3528649c8 memory_dff: Remove now-useless write port handling. 2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka bc717abad2 memory_dff: Remove code looking for $mux cells. 
This job is now performed by `opt_dff`, which runs before this pass.
 2021-03-08 16:58:12 +01:00
Marcelina Kościelnicka eb76d35e80 memory_dff: Fix needlessly duplicating enable bits. 
When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow.  Fix this by adding a simple cache.

Fixes #2409.
 2020-10-22 13:03:42 +02:00
Marcelina Kościelnicka 21896e2a02 memory_bram: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka 1e8098279f memory_map: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka d390b380e1 memory_unpack: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka e9978aaf15 memory_collect: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka 248b193d6d memory_nordff: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka c9251eb26b memory_dff: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka eae2edf3e4 memory_dff: recognize more dff cells 2020-07-23 20:55:28 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Xiretza edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
David Shah 85672a6c1f memory_bram: Fix ignorance of valid, matched rules 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-10 21:48:04 +01:00
whitequark 93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style 
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
 2020-04-10 14:51:01 +00:00
N. Engelhardt 7f33d43e3b
Merge pull request #1890 from boqwxp/cleanup_memory_collect 
Clean up `passes/memory/memory_collect.cc`.
 2020-04-09 14:01:29 +02:00
Alberto Gonzalez 652050b273
Clean up passes/memory/memory_collect.cc. 2020-04-09 05:43:05 +00:00
Alberto Gonzalez 685dc37d27
Clean up passes/memory/memory_unpack.cc. 2020-04-09 05:38:36 +00:00
whitequark e0def9e4d9 memory_map: add -attr option, to respect inference attributes. 
Before this commit, memory_map (which is always a part of a synth
script) would always pick up any $mem cell that was not processed
by a preceding pass and lower it down to $dff/$mux cells.
This is undesirable for two reasons:
  * If there is an explicit inference attribute set on a $mem cell,
    e.g. (* ram_block *), then it is arguably incorrect to map such
    a memory to $dff/$mux cells.
  * If memory_map tries to lower a memory that was intended to
    be mapped to a large BRAM, it often takes extraordinarily long
    time to finish, produces an extremely large log file, and outputs
    an unusable design.

After this commit, properly invoked memory_map will not map any
memory that has an explicit inference attribute specified, solving
the first issue, and alleviating the second. The default behavior
is not changed.
 2020-04-03 05:51:40 +00:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Eddie Hung 37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
Eddie Hung 1d93d1e59f memory_share: fix stray brace 2020-03-30 08:35:40 -07:00
Eddie Hung 4d897975a8 Code review fixes 2020-03-30 08:22:46 -07:00
Eddie Hung f64d59d824
Apply suggestions from code review 
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
 2020-03-30 08:19:56 -07:00
Eddie Hung 7ad7f41bc5 kernel: share a single CellTypes within a pass 2020-03-18 12:21:40 -07:00
Eddie Hung 432a09af80 kernel: SigSpec use more const& + overloads to prevent implicit SigSpec 2020-03-13 08:17:39 -07:00
whitequark 60f047f136 memory_bram: add attr_icase option. 
Some vendor toolchains use case insensitive matching for values of
attributes that control BRAM inference.
 2020-02-06 14:58:20 +00:00
Eddie Hung dccd7eb39f Cleanup 2019-12-17 00:25:08 -08:00
Eddie Hung 33e6d05585 Enforce non-existence 2019-12-16 17:06:30 -08:00
Eddie Hung 187e1c46e6 Update doc 2019-12-16 14:48:53 -08:00
Eddie Hung 4158ce4eda More sloppiness, thanks @dh73 for spotting 2019-12-16 13:56:45 -08:00
Eddie Hung 6b384861e4 Oops 2019-12-16 13:31:05 -08:00
Eddie Hung 503d1db551 Implement 'attributes' grammar 2019-12-16 12:58:13 -08:00
Diego H 87e21b0122 Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
Diego H b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Diego H 266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
Clifford Wolf 41e0ddf4f4
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr 
memory_collect: Copy attr from RTLIL::Memory to  cell
 2019-11-27 11:25:23 +01:00