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									 Clifford Wolf | a6370ce857 | Progress in xsthammer: working proof for cell models | 2013-06-10 14:02:11 +02:00 |  | 
				
					
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									 Clifford Wolf | d07b32ade5 | Progress on xsthammer | 2013-06-10 12:37:05 +02:00 |  | 
				
					
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									 Clifford Wolf | af83ed168e | Added first xsthammer scripts | 2013-06-10 01:40:20 +02:00 |  | 
				
					
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									 Clifford Wolf | cc05404128 | Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v | 2013-05-24 15:15:59 +02:00 |  | 
				
					
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									 Clifford Wolf | fbadb54b9b | Removed test cases that have been moved to yosys-test. https://github.com/cliffordwolf/yosys-tests/ | 2013-05-17 15:32:30 +02:00 |  | 
				
					
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									 Clifford Wolf | ff4a1dd06c | Improved vcdcd.pl (added -d option) | 2013-05-14 09:41:47 +02:00 |  | 
				
					
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									 Clifford Wolf | be8ecd6d16 | Some improvements in vcdcd.pl | 2013-05-14 08:50:59 +02:00 |  | 
				
					
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									 Clifford Wolf | e0c408cb4a | Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values | 2013-04-13 21:19:10 +02:00 |  | 
				
					
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									 Clifford Wolf | f1a2fd966f | Now only use value from "initial" when no matching "always" block is found | 2013-03-31 11:51:12 +02:00 |  | 
				
					
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									 Clifford Wolf | 5640b7d607 | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | 2013-03-31 11:17:56 +02:00 |  | 
				
					
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									 Clifford Wolf | 04843bdcbe | Added k68 (m68k compatible cpu) test case from verilator | 2013-03-31 11:00:46 +02:00 |  | 
				
					
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									 Clifford Wolf | d9bc024d29 | Renamed hansimem.v test case to mem_arst.v | 2013-03-24 15:25:08 +01:00 |  | 
				
					
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									 Clifford Wolf | c3c9e5a02f | Added hansimem testcase (memory with async reset) | 2013-03-24 10:40:40 +01:00 |  | 
				
					
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									 Clifford Wolf | e6cbeb5b16 | Set execute bit on tests/openmsp430/run-synth.sh for real | 2013-03-17 09:10:09 +01:00 |  | 
				
					
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									 Johann Glaser | a6f004e6f8 | set executable flags to run-synth.sh, added .gitignore Signed-off-by: Clifford Wolf <clifford@clifford.at> | 2013-03-17 09:06:02 +01:00 |  | 
				
					
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									 Johann Glaser | 3cfbc18601 | added ckeck for Icarus Verilog, otherwise the tests are silently stopped Signed-off-by: Clifford Wolf <clifford@clifford.at> | 2013-03-17 09:05:15 +01:00 |  | 
				
					
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									 Clifford Wolf | 2d9cbd3b02 | added more .gitignore files (make test) | 2013-01-05 11:35:52 +01:00 |  | 
				
					
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									 Clifford Wolf | 7764d0ba1d | initial import | 2013-01-05 11:13:26 +01:00 |  |