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Author	SHA1	Message	Date
Eddie Hung	2ca83005fb	abc9 to cope with multiple modules	2019-02-20 12:56:15 -08:00
Eddie Hung	d6b317b349	abc9 to use & syntax for -fast, and name fixes	2019-02-20 12:40:17 -08:00
Eddie Hung	f9702a8abe	read_aiger: new naming fixes	2019-02-20 12:39:51 -08:00
Eddie Hung	83b66861e9	read_aiger to name wires with internal name, less likely to clash	2019-02-20 11:22:56 -08:00
Eddie Hung	ef60ca1717	write_xaiger to not write latches, CO/PO fixes	2019-02-20 11:09:13 -08:00
Eddie Hung	45ddd9066e	synth to take -abc9 argument	2019-02-20 11:08:49 -08:00
Clifford Wolf	84999a7e68	Add ice40 test_dsp_map test case generator ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-20 17:18:59 +01:00
Clifford Wolf	218e9051bb	Add "synth_ice40 -dsp" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-20 16:42:27 +01:00
Clifford Wolf	246391200e	Add FF support to wreduce ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-20 16:36:42 +01:00
Clifford Wolf	7bf4e4a185	Improve iCE40 SB_MAC16 model ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-20 12:55:20 +01:00
Clifford Wolf	dca65d83a0	Detect and reject cases that do not map well to iCE40 DSPs (yet) ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-20 11:18:19 +01:00
Eddie Hung	62e5ff9ba8	abc9 to cope with indexed wires when creating $lut from $_NOT_	2019-02-19 16:06:03 -08:00
Eddie Hung	d365682a21	Add aiger tests to make tests	2019-02-19 15:25:47 -08:00
Eddie Hung	ef1a1402bc	Add a quick abc9 test	2019-02-19 15:25:03 -08:00
Eddie Hung	7b026c4bc3	Same for ascii AIGERs too	2019-02-19 15:15:50 -08:00
Eddie Hung	d304882cba	read_aiger to cope with non-unique POs	2019-02-19 15:14:08 -08:00
Jim Lawson	5c4a72c43e	Fix normal (non-array) hierarchy -auto-top. ... Add simple test.	2019-02-19 14:35:15 -08:00
Eddie Hung	f9af902532	Merge branch 'master' into xaig	2019-02-19 14:20:04 -08:00
Eddie Hung	92b60d5e42	Merge branch 'master' into read_aiger	2019-02-19 12:36:10 -08:00
Eddie Hung	78873d5bbb	Merge branch 'master' into read_aiger	2019-02-19 12:33:22 -08:00
Eddie Hung	2a8e5bf953	Merge pull request #805 from eddiehung/dff_init ... write_verilog to write initial statement for initial flop state	2019-02-19 12:32:40 -08:00
Eddie Hung	8158bc3f99	abc9 to replace $_NOT_ with $lut	2019-02-19 12:30:20 -08:00
Eddie Hung	e79df5e70e	read_aiger to create sane $lut names, and rename when renaming driving wire	2019-02-19 12:27:50 -08:00
David Shah	bb56cb738d	ecp5: Add DDRDLLA ... Signed-off-by: David Shah <davey1576@gmail.com>	2019-02-19 19:34:37 +00:00
Eddie Hung	0b1fc46ae3	Add comment	2019-02-19 10:24:55 -08:00
Eddie Hung	54f719f446	Get rid of boost dep, fix the FIXMEs for Win32?	2019-02-19 10:19:53 -08:00
Eddie Hung	843e7fc8a7	Fix for using POSIX basename	2019-02-19 09:02:37 -08:00
David Shah	c36f15b489	ecp5: Add DELAYF/DELAYG blackboxes ... Signed-off-by: David Shah <davey1576@gmail.com>	2019-02-19 14:10:43 +00:00
Clifford Wolf	62493c91b2	Add first draft of functional SB_MAC16 model ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-19 14:47:27 +01:00
Eddie Hung	8e1dbfac3a	Missing OSX headers?	2019-02-17 20:59:53 -08:00
Eddie Hung	de1dc7947b	Revert "Missing headers for Xcode?" ... This reverts commit c23e3f0751.	2019-02-17 20:59:15 -08:00
Eddie Hung	3af8d420c5	Merge branch 'dff_init' into read_aiger	2019-02-17 20:49:56 -08:00
Eddie Hung	11480b4fa3	Instead of INIT param on cells, use initial statement with hier ref as ... per @cliffordwolf	2019-02-17 12:18:12 -08:00
Eddie Hung	3d3353e020	Revert "Add INIT parameter to all ff/latch cells" ... This reverts commit 742b4e01b4.	2019-02-17 12:11:52 -08:00
Eddie Hung	9268a271fb	read_aiger to ignore line after ands for ascii, not binary	2019-02-17 12:07:14 -08:00
Eddie Hung	430a7548bc	One more merge conflict	2019-02-17 11:50:55 -08:00
Eddie Hung	144c5d4359	Merge branch 'dff_init' into read_aiger	2019-02-17 11:49:13 -08:00
Eddie Hung	17cd5f759f	Merge https://github.com/YosysHQ/yosys into dff_init	2019-02-17 11:49:06 -08:00
Eddie Hung	03a533d102	Merge https://github.com/YosysHQ/yosys into read_aiger	2019-02-17 11:44:01 -08:00
Clifford Wolf	5a853ed46c	Add actual DSP inference to ice40_dsp pass ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-02-17 15:35:48 +01:00
Clifford Wolf	c06c062469	Merge branch 'master' of github.com:YosysHQ/yosys into pmgen	2019-02-17 12:10:19 +01:00
Clifford Wolf	e45f62b0c5	Merge pull request #811 from ucb-bar/firrtlfixes ... Update cells supported for verilog to FIRRTL conversion.	2019-02-17 11:39:14 +01:00
Eddie Hung	45d49d5d14	Get rid of debugging stuff in abc9	2019-02-16 22:25:22 -08:00
Eddie Hung	82459c16c4	In read_xaiger, do not construct ConstEval for every LUT	2019-02-16 22:22:29 -08:00
Eddie Hung	30f1204721	Cleanup	2019-02-16 22:22:17 -08:00
Eddie Hung	f60cd4ff9b	read_aiger to ignore output = input of same wire; also create new output for different wire	2019-02-16 21:53:03 -08:00
Eddie Hung	76c35f80f4	Cleanup	2019-02-16 21:09:48 -08:00
Eddie Hung	6a57de9013	write_xaiger to support non-bit cell connections, and cope with COs for -O	2019-02-16 21:00:39 -08:00
Eddie Hung	f853b2f3c1	abc9 to write_aiger with -O option, and ignore dummy outputs	2019-02-16 20:09:40 -08:00
Eddie Hung	b9a305b85d	write_aiger -O to write dummy output as __dummy_o__	2019-02-16 20:08:59 -08:00