1233 commits

Author	SHA1	Message	Date
Clifford Wolf	a51a3fa2d2	Added echo command	2014-02-07 14:17:00 +01:00
Clifford Wolf	fa295a4528	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	2014-02-06 19:22:46 +01:00
Clifford Wolf	1c6dea3a0d	Added support for #-comments in same line as command	2014-02-06 14:26:39 +01:00
Clifford Wolf	19029f377b	Added support for backslash continuation in script files	2014-02-06 01:28:33 +01:00
Clifford Wolf	d267bcde4e	Fixed bug in sequential sat proofs and improved handling of asserts	2014-02-04 12:46:16 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	f9c4d33909	Added RTLIL::SigSpec::to_single_sigbit()	2014-02-02 21:35:26 +01:00
Clifford Wolf	672229eda5	Added yosys -H for command list	2014-01-30 12:32:59 +01:00
Clifford Wolf	96084e9864	Added -h command line option	2014-01-29 11:10:39 +01:00
Clifford Wolf	c36bac0e10	Added $assert support to satgen	2014-01-19 15:37:56 +01:00
Clifford Wolf	1e67099b77	Added $assert cell	2014-01-19 14:03:40 +01:00
Clifford Wolf	548d5aafa4	Some improvements in log_dump_val_worker() templates	2014-01-17 23:14:17 +01:00
Clifford Wolf	651ce67d97	Added select -assert-none and -assert-any	2014-01-17 16:34:50 +01:00
Clifford Wolf	7354a1718e	Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux	2014-01-03 17:30:50 +01:00
Clifford Wolf	eec2cd1e78	Added RTLIL::SigSpec::optimized() API	2014-01-03 02:43:31 +01:00
Clifford Wolf	fb2bf934dc	Added correct handling of $memwr priority	2014-01-03 00:22:17 +01:00
Clifford Wolf	1f80557ade	Added SAT undef model for $pmux and $safe_pmux	2014-01-02 19:58:59 +01:00
Clifford Wolf	249ef8695a	Major rewrite of "freduce" command	2014-01-02 16:52:33 +01:00
Clifford Wolf	15acf593e7	Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint	2013-12-31 14:54:06 +01:00
Clifford Wolf	bf607df6d5	Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)	2013-12-29 17:39:49 +01:00
Clifford Wolf	c69c416d28	Added $bu0 cell (for easy correct $eq/$ne mapping)	2013-12-28 12:02:14 +01:00
Clifford Wolf	122b3c067b	Fixed sat handling of $eqx and $nex with unequal port widths	2013-12-27 18:11:05 +01:00
Clifford Wolf	0f5ab7649e	Small cleanup in SatGen	2013-12-27 15:18:14 +01:00
Clifford Wolf	ebf9abfeb6	Fixed sat handling of $eqx and $nex cells	2013-12-27 14:32:42 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	2ee3ac4ba3	Added log_dump() API	2013-12-20 12:11:58 +01:00
Clifford Wolf	8a815ac741	Added "sat" undef support and "sat -set-init" options	2013-12-07 17:28:51 +01:00
Clifford Wolf	ccf083e5b0	Fixed uninitialized const flags bug	2013-12-07 16:56:34 +01:00
Clifford Wolf	5d83904746	Fixes and improvements in RTLIL::SigSpec::parse	2013-12-07 11:57:29 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	a66ca0472a	Added Pass:call_newsel API	2013-12-02 12:17:04 +01:00
Clifford Wolf	905eac04f1	Added "history" command	2013-12-02 11:29:39 +01:00
Clifford Wolf	1b3a60976d	Using RTLIL::id2cstr for prompt printing	2013-11-29 11:55:18 +01:00
Clifford Wolf	61412d167f	Improvements in satgen undef handling	2013-11-25 16:50:45 +01:00
Clifford Wolf	bd65e67d8a	Improvements in satgen undef handling	2013-11-25 15:12:01 +01:00
Clifford Wolf	8c3f4b3957	Started implementing undef handling in satgen	2013-11-25 04:51:33 +01:00
Clifford Wolf	8dafecd34d	Added module->avail_parameters (for advanced techmap features)	2013-11-24 20:29:07 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	532091afcb	Added more generic _TECHMAP_ wire mechanism to techmap pass	2013-11-23 15:58:06 +01:00
Clifford Wolf	c854ad2e7e	Some driver changes/fixes	2013-11-22 14:53:57 +01:00
Clifford Wolf	058ceda6a0	Added more performance measurement infrastructure	2013-11-22 14:08:10 +01:00
Clifford Wolf	18d003254c	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	2013-11-22 04:41:20 +01:00
Clifford Wolf	8e58bb330d	Added SigBit struct and refactored RTLIL::SigSpec::extract	2013-11-22 04:07:13 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	7d52eb0ddb	Added -v<level> option and some minor driver cleanups	2013-11-17 13:26:31 +01:00
Clifford Wolf	0fd3ebdb23	Added information on all internal cell types to internal checker	2013-11-11 00:13:18 +01:00
Clifford Wolf	378cc509cd	Call internal checker more often	2013-11-10 23:24:21 +01:00