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Author SHA1 Message Date
whitequark
13b2963ded ilang_lexer: fix check for out of range literal. 
Commit ca70a104 did not use a correct check.
 2020-05-29 06:58:44 +00:00
whitequark
0d99522b3c
Merge pull request #2095 from rswarbrick/hier-typo 
Fix small typos in documentation for hierarchy command
 2020-05-28 10:49:14 +00:00
Rupert Swarbrick
1158bbf7db Fix small typos in documentation for hierarchy command 2020-05-28 11:39:44 +01:00
whitequark
abac0ab28e
Merge pull request #2091 from boqwxp/printattrs 
Add `printattrs` command to print attributes of currently selected objects.
 2020-05-28 10:25:34 +00:00
whitequark
2384a59e2a
Merge pull request #2051 from Xiretza/makefile-cd-warning 
Suppress warning during initial clone of ABC repo
 2020-05-28 10:00:49 +00:00
whitequark
736ccb2ad5
Merge pull request #2031 from epfl-vlsc/master 
Add extmodule support to firrtl backend
 2020-05-28 09:59:17 +00:00
whitequark
2974183855
Merge pull request #2063 from boqwxp/techmapped-firrtl 
firrtl: Accept techmapped cell types in FIRRTL backend.
 2020-05-28 09:42:58 +00:00
whitequark
02bb52eef1
Merge pull request #2088 from rswarbrick/count-at 
Minor optimisation in Module::wire() and Module::cell()
 2020-05-28 09:41:17 +00:00
whitequark
fdca785eda
Merge pull request #2087 from rswarbrick/lex-warn 
Silence spurious warning in Verilog lexer when compiling with GCC
 2020-05-28 09:41:04 +00:00
whitequark
8a44a46806
Merge pull request #2086 from rswarbrick/sigbit 
Use default copy constructor for RTLIL::SigBit
 2020-05-28 09:40:49 +00:00
whitequark
5b62dbb0af
Merge pull request #2084 from rswarbrick/c_str 
Use c_str(), not str() for IdString/std::string == and != operators
 2020-05-28 09:40:35 +00:00
Alberto Gonzalez
5896ffd56f
printattrs: Simplify get_indent_str(). 
Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
 2020-05-28 05:34:28 +00:00
Alberto Gonzalez
f671c99cb8
printattrs: Refactor indentation string building for clarity. 
Co-Authored-By: whitequark <whitequark@whitequark.org>
 2020-05-27 23:15:07 +00:00
Alberto Gonzalez
6228b10c9f
printattrs: Add test. 2020-05-27 08:00:00 +00:00
Alberto Gonzalez
e50e4ee285
printattrs: Use flags to pretty-print the RTLIL::Const appropriately. 
Co-Authored-By: whitequark <whitequark@whitequark.org>
 2020-05-27 08:00:00 +00:00
Alberto Gonzalez
b8365547e9
misc: Add printattrs command. 2020-05-27 08:00:00 +00:00
whitequark
b651352193
Merge pull request #2090 from whitequark/cxxrtl-fixes 
Minor fixes for CXXRTL
 2020-05-26 22:18:14 +00:00
whitequark
0bf6b164be cxxrtl: make logging a little bit nicer. 2020-05-26 21:37:32 +00:00
whitequark
e9c07e2bda cxxrtl: add missing parts of commit 281c9685. 2020-05-26 21:34:20 +00:00
Rupert Swarbrick
6aa0f72ae9 Silence spurious warning in Verilog lexer when compiling with GCC 
The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
 2020-05-26 17:54:57 +01:00
Rupert Swarbrick
7ff306ccdb Minor optimisation in Module::wire() and Module::cell() 
The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.

Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().

Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.
 2020-05-26 16:07:36 +01:00
Rupert Swarbrick
17b5f23f20 Use default copy constructor for RTLIL::SigBit 
There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).

This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.
 2020-05-26 13:18:01 +01:00
Rupert Swarbrick
8f87ccec9b Use c_str(), not str() for IdString/std::string == and != operators 
These operators work by fetching the string from the global string
table and then comparing with the std::string that was passed in as
rhs.

Using str() means that we create a std::string (strlen; malloc;
memcpy), compare for equality (another memcmp if they have the same
length) and then finally free the string.

Using c_str() means that we pass the const char* straight to
std::string's equality operator. This ends up as a call to
std::string::compare (the const char* flavour), which is essentially
strcmp.
 2020-05-26 12:27:15 +01:00
Eddie Hung
a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy 
xilinx: tidy up cells_sim.v a little
 2020-05-25 14:21:10 -07:00
Eddie Hung
08221edbc1 tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00
Eddie Hung
5b81df57c8 xilinx: tidy up cells_sim.v a little 2020-05-25 09:48:11 -07:00
Eddie Hung
59b355fb85
Merge pull request #2044 from YosysHQ/eddie/fix2037 
verilog: allow attributes on behavioural statements (including null statement)
 2020-05-25 09:14:00 -07:00
Eddie Hung
c5a9abba11 verilog: move attr from simple_behav_stmt to its children to attach 2020-05-25 07:36:53 -07:00
Eddie Hung
95dcd7e785 test: add attribute-before-stmt test from @nakengelhardt 2020-05-25 07:36:53 -07:00
Eddie Hung
1c117ac023 verilog: do not warn for attributes on null statements 2020-05-25 07:36:53 -07:00
Eddie Hung
29d84339bf tests: add an generate-else test too 2020-05-25 07:36:53 -07:00
Eddie Hung
88bddb37c9 verilog: handle empty generate statement by removing gen_stmt_or_null... 
... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
 2020-05-25 07:36:53 -07:00
Eddie Hung
d21a07c7b5 verilog: fix #2037 by permitting (and freeing) attributes on null stmt 2020-05-25 07:36:53 -07:00
Eddie Hung
589775538c tests: add #2037 testcase 2020-05-25 07:36:53 -07:00
clairexen
ae11156c90
Merge pull request #2015 from boqwxp/qbfsat-bisection 
qbfsat: Add an iterative bisection optimization method and make it the default.
 2020-05-25 15:50:18 +02:00
Eddie Hung
89ed34fe55
Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanup 
xaiger: do not derive cells
 2020-05-24 10:10:50 -07:00
Eddie Hung
33b03ce904 xaiger: add testcase 2020-05-24 08:48:23 -07:00
Eddie Hung
d64df21630 xaiger: do not derive cells 2020-05-24 08:17:30 -07:00
Eddie Hung
227c3ff310
Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanup 
ecp5: cleanup unused +/ecp5/abc9_model.v
 2020-05-23 09:28:42 -07:00
Eddie Hung
76e0cc8276 ecp5: cleanup unused +/ecp5/abc9_model.v 2020-05-23 08:17:40 -07:00
Alberto Gonzalez
ac41f8a9c7
qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d6. 2020-05-23 00:53:09 +00:00
Alberto Gonzalez
aea0fd5ed4
qbfsat: Add bisection mode and make it the default. 
Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.
 2020-05-23 00:53:09 +00:00
whitequark
721040df76
Merge pull request #2072 from whitequark/cxxrtl-dont-purge 
cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level
 2020-05-22 20:08:39 +00:00
whitequark
281c96856a cxxrtl: get rid of -O5 aka opt_clean -purge optimization level. 
This isn't actually necessary anymore after scheduling was improved,
and `clean -purge` disrupts the mapping between wires in the input
RTLIL netlist and the output CXXRTL code.
 2020-05-22 19:08:30 +00:00
Eddie Hung
4f0f321169 abc9_ops: update comment 2020-05-21 21:39:13 -07:00
Eddie Hung
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr 
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
 2020-05-21 11:00:36 -07:00
Eddie Hung
38e858af8d
Update frontends/verilog/verilog_parser.y 
Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
 2020-05-21 09:10:56 -07:00
Miodrag Milanović
637650597b
Merge pull request #2059 from boqwxp/logger-vector-to-dict 
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
 2020-05-21 15:36:30 +02:00
N. Engelhardt
026fed3135
Merge pull request #2046 from PeterCrozier/trap 
Extend YS_DEBUGTRAP to MacOS.
 2020-05-20 10:12:24 +02:00
N. Engelhardt
7c4e580f8f
Merge pull request #2054 from boqwxp/fix-smtbmc 
smtbmc: Fix return status handling.
 2020-05-20 08:55:36 +02:00