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Code Activity
7709 commits 98 branches 53 tags 41 MiB
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45 commits

Author SHA1 Message Date
Miodrag Milanovic e6ad714d20 hierarchy - proc reorder 2019-10-18 08:06:57 +02:00
Miodrag Milanovic 980df499ab Make equivalence work with latest master 2019-10-17 17:24:53 +02:00
Miodrag Milanovic b2f0d75807 remove not needed top module 2019-10-17 17:11:11 +02:00
Miodrag Milanovic 1a399c6456 remove not needed top module 2019-10-17 17:11:11 +02:00
Miodrag Milanovic a198bcdd4f split muxes synth per type 2019-10-17 17:11:11 +02:00
Miodrag Milanovic 36af102801 Test dffs separetely 2019-10-17 17:11:11 +02:00
Miodrag Milanovic 487b38b124 Split latches into separete tests 2019-10-17 17:11:11 +02:00
Miodrag Milanovic fba6229718 Fix formatting 2019-10-17 17:10:42 +02:00
Miodrag Milanovic 53bc499a90 Clean verilog code from not used define block 2019-10-17 17:10:42 +02:00
Miodrag Milanovic d37cd267a5 Removed alu and div_mod test as agreed, ignore generated files 2019-10-17 17:10:42 +02:00
Miodrag Milanovic a7fbc8c3fe Test per flip-flop type 2019-10-17 17:10:42 +02:00
Eddie Hung 3b44084320 Add -assert 2019-10-17 17:10:42 +02:00
Eddie Hung 8422ad3e3a Use built-in async2sync call as per #1417 2019-10-17 17:10:42 +02:00
Eddie Hung 5b7bc3ab85 Update mul test to DSP48E1 2019-10-17 17:10:02 +02:00
Eddie Hung 08bd1816e3 Update area for div_mod 2019-10-17 17:10:02 +02:00
Eddie Hung a12801843b Add comment for lack of tristate logic pointing to #1225 2019-10-17 17:10:02 +02:00
Eddie Hung eded90b6b4 Move $x to end as 7f0eec8 2019-10-17 17:10:02 +02:00
SergeyDegtyar 305672170b adffs test update (equiv_opt -multiclock) 2019-10-17 17:10:02 +02:00
Sergey bb70eb977d Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey 68f9239c57 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey df6d0b95da Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey c340d54657 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey 205f52ffe5 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey df7fe40529 Fix div_mod test 2019-10-17 17:10:02 +02:00
SergeyDegtyar 7bc8f0c2e2 Add comment with expected behavior for latches,tribuf tests;Update adffs test 2019-10-17 17:10:02 +02:00
SergeyDegtyar 489444bcba Fix latches.ys test 2019-10-17 17:10:02 +02:00
SergeyDegtyar 757c476f62 Add smoke tests to tests/xilinx 2019-10-17 17:10:02 +02:00
Eddie Hung 5d680590d6 Use equiv_opt -async2sync for xilinx 2019-10-03 10:30:33 -07:00
Eddie Hung 6216e45eda Add latch test modified from #1363 2019-09-30 12:52:43 +02:00
Eddie Hung 2f98f9deee Add mac.sh and macc_tb.v for testing 2019-09-19 18:08:16 -07:00
Eddie Hung c663a3680b Remove stat 2019-09-18 12:44:34 -07:00
Eddie Hung c9fe4d7992 Add .gitignore 2019-09-18 12:11:33 -07:00
Eddie Hung c3cba7ab93 Refine macc testcase 2019-09-18 12:07:25 -07:00
Eddie Hung 7d644f40ed Add AREG=2 BREG=2 test 2019-09-11 17:05:47 -07:00
Eddie Hung 6a95ecd41d Update test with a/b reset 2019-09-11 10:13:13 -07:00
Eddie Hung 36d6db7f8a Extend test for RSTP and RSTM 2019-09-11 09:09:08 -07:00
Eddie Hung 1fc50a03fc Add SIMD test 2019-09-09 21:40:06 -07:00
Eddie Hung e68507a716 Update macc test 2019-09-06 23:19:03 -07:00
Eddie Hung 9be9631e5a Add macc test, with equiv_opt not currently passing 2019-08-30 16:18:14 -07:00
Eddie Hung d508dc2906 Update test for ffM 2019-08-30 15:01:08 -07:00
Eddie Hung 7df0e77565 Add mul_unsigned test 2019-08-30 14:35:05 -07:00
Eddie Hung 64ea147236 Add .gitignore 2019-08-28 09:55:34 -07:00
Eddie Hung 2f493fb465 Use test_pmgen for xilinx_srl 2019-08-28 09:55:09 -07:00
Eddie Hung 2e9e745efa Do not simplemap for variable test 2019-08-28 09:26:08 -07:00
Eddie Hung 975aaf190f Add xilinx_srl test 2019-08-28 09:24:19 -07:00