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Code Activity
13648 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
chunlin min
0afb5e28fb cosmetic changes 2024-07-08 15:10:44 -04:00
chunlin min
af67c745c4 initialize argidx to 1 2024-07-08 11:41:41 -04:00
chunlin min
a0c9d10118 undo last change, to investigate dff_opt test failure 2024-07-08 11:30:52 -04:00
chunlin min
3c95a28dc2 fix compile warning 2024-07-08 11:13:53 -04:00
Tony Min
d41688f7d7
Revisions (#4) 
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
 2024-07-08 10:57:16 -04:00
Tony Min
6fe0e00050
Add missing u sram init (#3) 
add missing INIT for uSRAM
 2024-07-04 16:39:10 -04:00
Tony Min
e9ff5f7d91
Merge pull request #2 from tony-min-1/move_tests 
Move tests
 2024-07-04 16:05:04 -04:00
chunlin min
9de5602574 ininclude microchip tests in makefile 2024-07-04 15:54:59 -04:00
chunlin min
8e7ec2d660 add assertions for synth_microchip tests 2024-07-04 15:45:44 -04:00
chunlin min
e3c4791e5b move microchip tests from techlibs/microchip/tests to tests/arch/microchip 2024-07-04 14:16:52 -04:00
chunlin min
19d3214861 use output reg instead of additional reg declaration 2024-07-04 14:13:26 -04:00
Tony Min
7ff8912338
Merge pull request #1 from tony-min-1/change_filenames 
changes made to filenames + references
 2024-07-04 14:04:36 -04:00
C77874
5ba06fd947 another typo 2024-07-04 10:33:59 -07:00
C77874
6b80e02d62 missed a few pf instances 2024-07-04 10:25:15 -07:00
C77874
c385421c17 rename options 2024-07-04 09:45:04 -07:00
C77874
d0cd01adfe fixed typos, build with makefile succeeds 2024-07-04 09:33:58 -07:00
C77874
59e45be275 Merge branch 'mchp' of https://github.com/tony-min-1/yosys into change_filenames 2024-07-04 09:00:38 -07:00
C77874
0bb7d1373f changes made to filenames + references 2024-07-04 08:53:41 -07:00
Chun Lin Min
7770fa70e1 fix cells_sim.v 2024-07-04 05:20:22 -07:00
Chun Lin Min
e5bdc9b5c9 remove DSP48 references 2024-07-03 07:20:29 -07:00
Chun Lin Min
f57b624281 fix indent 2024-07-02 13:54:36 -07:00
Chun Lin Min
68a11c9941 more indent fix 2024-07-02 13:51:48 -07:00
Chun Lin Min
2ced2752e9 replace space indent with tab indent 2024-07-02 13:47:18 -07:00
Chun Lin Min
acddc36389 add PolarFire FPGA support 2024-07-02 12:44:30 -07:00
github-actions[bot]
a739e21a5f Bump version 2024-06-29 00:16:56 +00:00
Catherine
580aaa362d
opt_lut_ins: fix name of global object. NFCI 2024-06-28 15:12:36 +00:00
Martin Povišer
07daf61ae6
Merge pull request #4467 from povik/fix-add-shiftx 
rtlil: Fix `addShiftx` for signed shifts
 2024-06-26 18:17:28 +02:00
github-actions[bot]
1288166f7a Bump version 2024-06-25 00:17:11 +00:00
Miodrag Milanović
1e401c3e04
Merge pull request #4460 from YosysHQ/micko/c++17 
Make C++17 compiler required
 2024-06-24 19:54:30 +02:00
Miodrag Milanovic
777624ccf5 Make yosys-config dependant of Makefile 2024-06-24 16:08:08 +02:00
Martin Povišer
89d939334e rtlil: Fix addShiftx for signed shifts 
Only the `B` input (the shift amount) can be marked as signed on a
`$shiftx` cell. Adapt the helper accordingly and prevent it from
creating invalid RTLIL when called with `is_signed` set. Previously
it would mark both `A` and `B` as signed.
 2024-06-21 15:14:08 +02:00
github-actions[bot]
6c8ae44ae7 Bump version 2024-06-20 00:17:08 +00:00
gatecat
22d8df1e7e liberty: Support for IO liberty files for verification 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-06-19 21:12:42 +02:00
github-actions[bot]
ede3750a6c Bump version 2024-06-19 00:17:13 +00:00
Miodrag Milanović
8024688b1d
Merge pull request #4459 from YosysHQ/micko/vanilla_verific 
Verific build support improvements
 2024-06-18 10:50:20 +02:00
Miodrag Milanovic
2bbf3112d9 Update VS build to C++17 build 2024-06-17 17:29:20 +02:00
Martin Povišer
f9b7b8fff0 Update documentation for C++17 switch 2024-06-17 17:08:13 +02:00
Miodrag Milanovic
141a2e3638 Make C++17 compiler required 2024-06-17 16:55:36 +02:00
Miodrag Milanovic
dfde792288 Refactored import code 2024-06-17 14:49:58 +02:00
Miodrag Milanovic
19da7f7d59 Update makefile to make options uniform 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
0f3f731254 Handle -work for vhdl, and clean messages 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
0a81c8e161 Import all modules from all libraries when when needed 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
7c3094633d Compile with hier_tree separate SV and VHDL as well 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
e2e189647f Cleanup 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
7bec332b68 SV + VHDL with RTL support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
25d50bb2af VHDL only build support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic
54bf9ccf06 Add initial support for Verific without additional YosysHQ patch 2024-06-17 13:29:11 +02:00
N. Engelhardt
74a1dd99ac
Merge pull request #4444 from YosysHQ/krys/scripting_docs 
Document script parsing
 2024-06-14 09:53:24 +02:00
github-actions[bot]
2fd2b6538d Bump version 2024-06-14 00:17:13 +00:00
Asherah Connor
62bff3a204 cxxrtl: don't need to specify a value for "path". 
Callers of the deprecated method had a path already.
 2024-06-13 13:17:02 +01:00