mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
Code Activity

another typo

Browse source
This commit is contained in:
C77874 2024-07-04 10:33:59 -07:00
parent 6b80e02d62
commit 5ba06fd947
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
techlibs/microchip/tests/mac/mac.ys
View file

@ -18,7 +18,7 @@
read_verilog mac.v
# run the synth flow, specifies top module and additional parameters
synticrochip -top mac -abc9 -family polarfire -noiopad
synth_microchip -top mac -abc9 -family polarfire -noiopad
# write final outputfile
write_verilog -noexpr mac.vm