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Code Activity
15697 commits 122 branches 59 tags 72 MiB
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2441 commits

Author SHA1 Message Date
Eddie Hung
4da25c76b3 Ooopsie 2019-06-03 09:33:42 -07:00
Eddie Hung
9f44a71715 Consistent with xilinx 2019-06-03 09:23:43 -07:00
Eddie Hung
2228cef62f Add flops as blackboxes 2019-05-31 18:11:46 -07:00
Eddie Hung
01f71085f2 Add FD*E_1 -> FD*E techmap rules 2019-05-31 18:11:24 -07:00
Eddie Hung
dea36d4366 Techmap flops before ABC again 2019-05-31 18:10:25 -07:00
Eddie Hung
eb08e71bd1 Merge branch 'xaig' into xc7mux 2019-05-31 13:03:03 -07:00
Eddie Hung
1ad33c3b5a Remove whitebox attribute from DRAMs for now 2019-05-30 13:07:29 -07:00
Eddie Hung
fdfc18be91 Carry in/out to be the last input/output for chains to be preserved 2019-05-30 01:23:36 -07:00
Eddie Hung
276f5f8b81 Some more realistic delays... 2019-05-29 22:55:34 -07:00
Eddie Hung
f228621b80 Typo 2019-05-28 09:36:01 -07:00
Eddie Hung
e032e5bcde Make MUXF{7,8} and CARRY4 whitebox 2019-05-27 23:09:06 -07:00
Eddie Hung
54e28eb3ea Re-enable lib_whitebox 2019-05-27 23:08:55 -07:00
Eddie Hung
4311b9b583 Blackboxes 2019-05-26 11:32:02 -07:00
Eddie Hung
66701c5fcc Muck about with LUT delays some more 2019-05-26 02:52:48 -07:00
Eddie Hung
ca5774ed40 Try new LUT delays 2019-05-24 20:39:55 -07:00
Eddie Hung
60af2ca94d Transpose CARRY4 delays 2019-05-24 14:09:15 -07:00
Eddie Hung
52e9036d39 Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-23 13:38:04 -07:00
Eddie Hung
68359bcd6f Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux 2019-05-23 13:37:53 -07:00
Eddie Hung
99a3fee8f4 Add "min bits" and "min wports" to xilinx dram rules 2019-05-23 11:32:28 -07:00
Eddie Hung
ae89e6ab26 Add whitebox support to DRAM 2019-05-23 08:58:57 -07:00
Eddie Hung
4f44e3399b shift register inference before mux 2019-05-22 02:36:28 -07:00
Eddie Hung
9b1078b9bd Fix/workaround symptom unveiled by #1023 2019-05-21 18:50:02 -07:00
Eddie Hung
ee8435b820 Instead of MUXCY/XORCY use CARRY4 (with timing) 2019-05-21 16:19:45 -07:00
Eddie Hung
36a219063a Modify LUT area cost to be same as old abc 2019-05-21 14:31:19 -07:00
Eddie Hung
fb09c6219b Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-21 14:21:00 -07:00
Clifford Wolf
c4b8575f43 Add "wreduce -keepdc", fixes #1016 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-20 15:36:13 +02:00
Sylvain Munaut
4f9183d107 ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-05-13 12:51:06 +02:00
Clifford Wolf
04ef222cfb Add "stat -tech xilinx" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-11 09:24:52 +02:00
Ben Widawsky
05d8cc4567 Fix formatting for synth_intel.cc 
This is realized through the recently added .clang-format file.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-05-09 08:40:05 -07:00
Clifford Wolf
09467bb9a3 Add "synth_xilinx -arch" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-07 15:04:36 +02:00
Eddie Hung
d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Eddie Hung
c2e29ab809 Rename cells_map.v to prevent clash with ff_map.v 2019-05-03 14:40:32 -07:00
Clifford Wolf
373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff 
Improve pmgen, Add "peepopt" pass with shift-mul pattern
 2019-05-03 20:39:50 +02:00
Eddie Hung
283e33ba5a Trim off leading 1'bx in A 2019-05-02 16:02:37 -07:00
Eddie Hung
fc72f07efd Add don't care optimisation 2019-05-02 15:01:37 -07:00
Eddie Hung
d80445e049 Use new peepopt from #969 2019-05-02 11:35:57 -07:00
Eddie Hung
8829cba901 Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux 2019-05-02 11:25:34 -07:00
Eddie Hung
95867109ea Revert to pre-muxcover approach 2019-05-02 11:25:10 -07:00
Eddie Hung
d05ac7257e Missing help_mode 2019-05-02 11:14:28 -07:00
Eddie Hung
3b5e8c86a4 Fix -nocarry 2019-05-02 11:00:49 -07:00
Eddie Hung
5cd19b52da Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-02 10:44:59 -07:00
Eddie Hung
d394b9301b Back to passing all xc7srl tests! 2019-05-01 18:23:21 -07:00
Eddie Hung
31ff0d8ef5 Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine 2019-05-01 18:09:38 -07:00
Clifford Wolf
a27eeff573
Merge pull request #966 from YosysHQ/clifford/fix956 
Drive dangling wires with init attr with their init value
 2019-04-30 18:08:41 +02:00
Clifford Wolf
9d117eba9d Add handling of init attributes in "opt_expr -undriven" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 14:46:12 +02:00
Marcin Kościelnicki
98e5a625c4 synth_xilinx: Add -nocarry and -nomux options. 2019-04-30 12:54:21 +02:00
Clifford Wolf
d2d402e625 Run "peepopt" in generic "synth" pass and "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 08:10:37 +02:00
Eddie Hung
e97178a888 WIP 2019-04-28 12:51:00 -07:00
Eddie Hung
af840bbc63 Move neg-pol to pos-pol mapping from ff_map to cells_map.v 2019-04-28 12:36:04 -07:00
Eddie Hung
4aca928033 Fix spacing 2019-04-26 19:46:34 -07:00