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Code Activity
14651 commits 122 branches 59 tags 72 MiB
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1880 commits

Author SHA1 Message Date
Eddie Hung
08b55a20e3 module->derive() to be lazy and not touch ast if already derived 2019-09-30 14:11:01 -07:00
Eddie Hung
8684b58bed Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-30 12:29:35 -07:00
whitequark
5c5881695d
Merge pull request #1406 from whitequark/connect_rpc 
rpc: new frontend
 2019-09-30 17:38:20 +00:00
whitequark
99a7f39084 rpc: new frontend. 
A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.

Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
 2019-09-30 15:53:11 +00:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in 
Open aig frontend as binary file
 2019-09-30 17:49:23 +02:00
Eddie Hung
1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Miodrag Milanovic
9e55b234b4 Fix reading aig files on windows 2019-09-29 15:40:37 +02:00
Miodrag Milanovic
3f70c1fd26 Open aig frontend as binary file 2019-09-29 13:22:11 +02:00
Eddie Hung
79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Eddie Hung
8f5710c464 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-27 15:14:31 -07:00
Eddie Hung
c340fbfab2 Force $inout.out ports to begin with '$' to indicate internal 2019-09-23 21:58:04 -07:00
Clifford Wolf
8da0888bf6 Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-20 12:16:20 +02:00
Eddie Hung
b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext 
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
 2019-09-18 12:40:08 -07:00
Clifford Wolf
25b08b1afd Fix handling of range selects on loop variables, fixes #1372 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-16 11:25:37 +02:00
Clifford Wolf
a67d63714b Fix handling of z_digit "?" and fix optimization of cmp with "z" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-13 13:39:39 +02:00
Clifford Wolf
855e6a9b91 Fix lexing of integer literals without radix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-13 10:19:58 +02:00
Clifford Wolf
7eb593829f Fix lexing of integer literals, fixes #1364 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-12 09:43:32 +02:00
Eddie Hung
903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival 
Allow arrival times of sequential outputs to be specified to abc9
 2019-09-05 12:00:23 -07:00
Clifford Wolf
4b7202c9c2
Merge pull request #1350 from YosysHQ/clifford/fixsby59 
Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
 2019-09-05 18:14:28 +02:00
Eddie Hung
ba629e6a28 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-09-04 15:36:07 -07:00
Eddie Hung
d3eea82bc2 Revert "parse_xaiger() to do "clean -purge"" 
This reverts commit 5d16bf8316.
 2019-09-04 15:21:39 -07:00
Eddie Hung
d6a84a78a7 Merge remote-tracking branch 'origin/master' into eddie/deferred_top 2019-09-03 10:49:21 -07:00
Clifford Wolf
25e5fbac90 Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)" 
Fixes https://github.com/YosysHQ/SymbiYosys/issues/59

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-02 22:56:38 +02:00
Eddie Hung
c7f1ccbcb0 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 12:28:35 -07:00
Eddie Hung
5d16bf8316 parse_xaiger() to do "clean -purge" 2019-08-29 17:24:25 -07:00
Eddie Hung
83ffec26cb Remove newline 2019-08-29 09:08:58 -07:00
Eddie Hung
6510297712 Restore non-deferred code, deferred case to ignore non constant attr 2019-08-29 09:02:10 -07:00
Eddie Hung
34ae29295d read_verilog -defer should still populate module attributes 2019-08-28 19:59:09 -07:00
Eddie Hung
d672b1ddec Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-23 11:26:55 -07:00
Eddie Hung
fe1b2337fd Do not propagate mem2reg attribute through to result 2019-08-22 16:57:59 -07:00
Eddie Hung
a6776ee35e mem2reg to preserve user attributes and src 2019-08-21 13:36:01 -07:00
Eddie Hung
f1a206ba03 Revert "Remove sequential extension" 
This reverts commit 091bf4a18b.
 2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b Remove sequential extension 2019-08-20 18:16:37 -07:00
Eddie Hung
be9e4f1b67 Use abc_{map,unmap,model}.v 2019-08-20 12:39:11 -07:00
Eddie Hung
c4d4c6db3f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 12:00:12 -07:00
Clifford Wolf
c25c1e742b
Merge pull request #1308 from jakobwenzel/real_params 
Handle real values when deriving ast modules
 2019-08-20 11:37:26 +02:00
Eddie Hung
3f4886e7a3 Fix typo 2019-08-19 10:42:00 -07:00
Eddie Hung
2f4e0a5388 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-19 10:07:27 -07:00
Eddie Hung
9bfe924e17 Set abc_flop and use it in toposort 2019-08-19 09:40:01 -07:00
Jakob Wenzel
24971fda87 handle real values when deriving ast modules 2019-08-19 14:17:36 +02:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again 2019-08-18 08:04:10 +00:00
Clifford Wolf
2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255 
Fix various NDEBUG compiler warnings
 2019-08-17 15:07:16 +02:00
Clifford Wolf
27d59dc055 Fix erroneous ifndef-NDEBUG in verific.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 14:49:55 +02:00
Eddie Hung
24c934f1af Merge branch 'eddie/abc9_refactor' into xaig_dff 2019-08-16 16:51:22 -07:00
Eddie Hung
6b156beda1 Remove unused variable 2019-08-16 13:35:39 -07:00
Eddie Hung
847c54088e Change signature of parse_blif to take IdString 2019-08-15 10:26:24 -07:00
Clifford Wolf
0c5db07cd6 Fix various NDEBUG compiler warnings, closes #1255 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-13 13:29:03 +02:00
Eddie Hung
12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00