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yosys/frontends
whitequark 99a7f39084 rpc: new frontend.
A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.

Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
2019-09-30 15:53:11 +00:00
..
aiger Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext 2019-09-18 12:40:08 -07:00
ast Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360 2019-09-20 12:16:20 +02:00
blif Change signature of parse_blif to take IdString 2019-08-15 10:26:24 -07:00
ilang Allow attributes on individual switch cases in RTLIL. 2019-07-08 11:34:58 +00:00
json Update JSON front-end to process new attr/param encoding 2019-08-01 12:48:22 +02:00
liberty stoi -> atoi 2019-08-07 11:09:17 -07:00
rpc rpc: new frontend. 2019-09-30 15:53:11 +00:00
verific Fix erroneous ifndef-NDEBUG in verific.cc 2019-08-17 14:49:55 +02:00
verilog Fix handling of z_digit "?" and fix optimization of cmp with "z" 2019-09-13 13:39:39 +02:00