mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 21:27:00 +00:00
Merge branch 'eddie/abc9_refactor' into xaig_dff
This commit is contained in:
Eddie Hung
commit
24c934f1af
171 changed files with 6745 additions and 4523 deletions
|
|
@ -30,6 +30,7 @@
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#include <libkern/OSByteOrder.h>
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#define __builtin_bswap32 OSSwapInt32
|
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#endif
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#define __STDC_FORMAT_MACROS
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#include <inttypes.h>
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#include "kernel/yosys.h"
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@ -151,12 +152,12 @@ struct ConstEvalAig
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RTLIL::State eval_ret = RTLIL::Sx;
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if (cell->type == "$_NOT_") {
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if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1;
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else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0;
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if (sig_a == State::S0) eval_ret = State::S1;
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else if (sig_a == State::S1) eval_ret = State::S0;
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}
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else if (cell->type == "$_AND_") {
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if (sig_a == RTLIL::S0) {
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eval_ret = RTLIL::S0;
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if (sig_a == State::S0) {
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eval_ret = State::S0;
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goto eval_end;
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}
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@ -164,15 +165,15 @@ struct ConstEvalAig
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RTLIL::SigBit sig_b = cell->getPort("\\B");
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if (!eval(sig_b))
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return false;
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if (sig_b == RTLIL::S0) {
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eval_ret = RTLIL::S0;
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if (sig_b == State::S0) {
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eval_ret = State::S0;
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goto eval_end;
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}
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if (sig_a != RTLIL::S1 || sig_b != RTLIL::S1)
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if (sig_a != State::S1 || sig_b != State::S1)
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goto eval_end;
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eval_ret = RTLIL::S1;
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eval_ret = State::S1;
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}
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}
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else log_abort();
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@ -256,7 +257,7 @@ end_of_header:
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RTLIL::Wire* n0 = module->wire("\\__0__");
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if (n0)
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module->connect(n0, RTLIL::S0);
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module->connect(n0, State::S0);
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// Parse footer (symbol table, comments, etc.)
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unsigned l1;
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@ -301,7 +302,11 @@ static uint32_t parse_xaiger_literal(std::istream &f)
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uint32_t l;
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f.read(reinterpret_cast<char*>(&l), sizeof(l));
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if (f.gcount() != sizeof(l))
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#if defined(_WIN32) && defined(__MINGW32__)
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log_error("Offset %I64d: unable to read literal!\n", static_cast<int64_t>(f.tellg()));
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#else
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log_error("Offset %" PRId64 ": unable to read literal!\n", static_cast<int64_t>(f.tellg()));
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#endif
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return from_big_endian(l);
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}
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@ -333,7 +338,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
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return wire;
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}
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void AigerReader::parse_xaiger()
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void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
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{
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std::string header;
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f >> header;
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@ -367,22 +372,7 @@ void AigerReader::parse_xaiger()
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RTLIL::Wire* n0 = module->wire("\\__0__");
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if (n0)
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module->connect(n0, RTLIL::S0);
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dict<int,IdString> box_lookup;
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for (auto m : design->modules()) {
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auto it = m->attributes.find("\\abc_box_id");
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if (it == m->attributes.end())
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continue;
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if (m->name.begins_with("$paramod"))
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continue;
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auto id = it->second.as_int();
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auto r = box_lookup.insert(std::make_pair(id, m->name));
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if (!r.second)
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log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
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log_id(m), id, log_id(r.first->second));
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log_assert(r.second);
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}
|
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module->connect(n0, State::S0);
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|
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// Parse footer (symbol table, comments, etc.)
|
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std::string s;
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@ -534,9 +524,9 @@ void AigerReader::parse_aiger_ascii()
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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|
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if (l3 == 0)
|
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q_wire->attributes["\\init"] = RTLIL::S0;
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q_wire->attributes["\\init"] = State::S0;
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else if (l3 == 1)
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q_wire->attributes["\\init"] = RTLIL::S1;
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q_wire->attributes["\\init"] = State::S1;
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else if (l3 == l1) {
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//q_wire->attributes["\\init"] = RTLIL::Sx;
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}
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|
|
@ -545,7 +535,7 @@ void AigerReader::parse_aiger_ascii()
|
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}
|
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else {
|
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// AIGER latches are assumed to be initialized to zero
|
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q_wire->attributes["\\init"] = RTLIL::S0;
|
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q_wire->attributes["\\init"] = State::S0;
|
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}
|
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latches.push_back(q_wire);
|
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}
|
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|
|
@ -661,9 +651,9 @@ void AigerReader::parse_aiger_binary()
|
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
|
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|
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if (l3 == 0)
|
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q_wire->attributes["\\init"] = RTLIL::S0;
|
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q_wire->attributes["\\init"] = State::S0;
|
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else if (l3 == 1)
|
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q_wire->attributes["\\init"] = RTLIL::S1;
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q_wire->attributes["\\init"] = State::S1;
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else if (l3 == l1) {
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//q_wire->attributes["\\init"] = RTLIL::Sx;
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}
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@ -672,7 +662,7 @@ void AigerReader::parse_aiger_binary()
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}
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else {
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// AIGER latches are assumed to be initialized to zero
|
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q_wire->attributes["\\init"] = RTLIL::S0;
|
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q_wire->attributes["\\init"] = State::S0;
|
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}
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latches.push_back(q_wire);
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}
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@ -1044,16 +1034,17 @@ void AigerReader::post_process()
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}
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|
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module->fixup_ports();
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// Insert into a new (temporary) design so that "clean" will only
|
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// operate (and run checks on) this one module
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RTLIL::Design *mapped_design = new RTLIL::Design;
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mapped_design->add(module);
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Pass::call(mapped_design, "clean");
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mapped_design->modules_.erase(module->name);
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delete mapped_design;
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|
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design->add(module);
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|
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design->selection_stack.emplace_back(false);
|
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RTLIL::Selection& sel = design->selection_stack.back();
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sel.select(module);
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Pass::call(design, "clean");
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design->selection_stack.pop_back();
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|
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for (auto cell : module->cells().to_vector()) {
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if (cell->type != "$lut") continue;
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auto y_port = cell->getPort("\\Y").as_bit();
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@ -1124,8 +1115,8 @@ struct AigerFrontend : public Frontend {
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if (module_name.empty()) {
|
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#ifdef _WIN32
|
||||
char fname[_MAX_FNAME];
|
||||
_splitpath(filename.c_str(), NULL /* drive */, NULL /* dir */, fname, NULL /* ext */)
|
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module_name = fname;
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_splitpath(filename.c_str(), NULL /* drive */, NULL /* dir */, fname, NULL /* ext */);
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module_name = fname;
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#else
|
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char* bn = strdup(filename.c_str());
|
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module_name = RTLIL::escape_id(bn);
|
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|
|
|
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|
|
@ -47,7 +47,7 @@ struct AigerReader
|
|||
|
||||
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
|
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void parse_aiger();
|
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void parse_xaiger();
|
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void parse_xaiger(const dict<int,IdString> &box_lookup);
|
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void parse_aiger_ascii();
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void parse_aiger_binary();
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void post_process();
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|
|
|
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|
|
@ -283,8 +283,8 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
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if (!bits.empty()) {
|
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fprintf(f, " bits='");
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for (size_t i = bits.size(); i > 0; i--)
|
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fprintf(f, "%c", bits[i-1] == RTLIL::S0 ? '0' :
|
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bits[i-1] == RTLIL::S1 ? '1' :
|
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fprintf(f, "%c", bits[i-1] == State::S0 ? '0' :
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bits[i-1] == State::S1 ? '1' :
|
||||
bits[i-1] == RTLIL::Sx ? 'x' :
|
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bits[i-1] == RTLIL::Sz ? 'z' : '?');
|
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fprintf(f, "'(%d)", GetSize(bits));
|
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|
|
@ -716,7 +716,7 @@ AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
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node->integer = v;
|
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node->is_signed = is_signed;
|
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for (int i = 0; i < width; i++) {
|
||||
node->bits.push_back((v & 1) ? RTLIL::S1 : RTLIL::S0);
|
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node->bits.push_back((v & 1) ? State::S1 : State::S0);
|
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v = v >> 1;
|
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}
|
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node->range_valid = true;
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|
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@ -733,9 +733,9 @@ AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signe
|
|||
node->bits = v;
|
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for (size_t i = 0; i < 32; i++) {
|
||||
if (i < node->bits.size())
|
||||
node->integer |= (node->bits[i] == RTLIL::S1) << i;
|
||||
node->integer |= (node->bits[i] == State::S1) << i;
|
||||
else if (is_signed && !node->bits.empty())
|
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node->integer |= (node->bits.back() == RTLIL::S1) << i;
|
||||
node->integer |= (node->bits.back() == State::S1) << i;
|
||||
}
|
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node->range_valid = true;
|
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node->range_left = node->bits.size()-1;
|
||||
|
|
@ -767,7 +767,7 @@ AstNode *AstNode::mkconst_str(const std::string &str)
|
|||
for (size_t i = 0; i < str.size(); i++) {
|
||||
unsigned char ch = str[str.size() - i - 1];
|
||||
for (int j = 0; j < 8; j++) {
|
||||
data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
|
||||
data.push_back((ch & 1) ? State::S1 : State::S0);
|
||||
ch = ch >> 1;
|
||||
}
|
||||
}
|
||||
|
|
@ -780,7 +780,7 @@ AstNode *AstNode::mkconst_str(const std::string &str)
|
|||
bool AstNode::bits_only_01() const
|
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{
|
||||
for (auto bit : bits)
|
||||
if (bit != RTLIL::S0 && bit != RTLIL::S1)
|
||||
if (bit != State::S0 && bit != State::S1)
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
|
@ -1164,7 +1164,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
|
|||
}
|
||||
}
|
||||
|
||||
if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
|
||||
if (flag_icells && (*it)->str.compare(0, 2, "\\$") == 0)
|
||||
(*it)->str = (*it)->str.substr(1);
|
||||
|
||||
if (defer)
|
||||
|
|
@ -1463,7 +1463,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
|
|||
{
|
||||
std::string stripped_name = name.str();
|
||||
|
||||
if (stripped_name.substr(0, 9) == "$abstract")
|
||||
if (stripped_name.compare(0, 9, "$abstract") == 0)
|
||||
stripped_name = stripped_name.substr(9);
|
||||
|
||||
log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
|
||||
|
|
@ -1551,7 +1551,9 @@ RTLIL::Module *AstModule::clone() const
|
|||
new_mod->nomeminit = nomeminit;
|
||||
new_mod->nomem2reg = nomem2reg;
|
||||
new_mod->mem2reg = mem2reg;
|
||||
new_mod->noblackbox = noblackbox;
|
||||
new_mod->lib = lib;
|
||||
new_mod->nowb = nowb;
|
||||
new_mod->noopt = noopt;
|
||||
new_mod->icells = icells;
|
||||
new_mod->pwires = pwires;
|
||||
|
|
|
|||
|
|
@ -1516,7 +1516,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
AstNode *child = *it;
|
||||
if (child->type == AST_CELLTYPE) {
|
||||
cell->type = child->str;
|
||||
if (flag_icells && cell->type.substr(0, 2) == "\\$")
|
||||
if (flag_icells && cell->type.begins_with("\\$"))
|
||||
cell->type = cell->type.substr(1);
|
||||
continue;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2319,7 +2319,7 @@ skip_dynamic_range_lvalue_expansion:;
|
|||
if (attr.first.str().rfind("\\via_celltype_defparam_", 0) == 0)
|
||||
{
|
||||
AstNode *cell_arg = new AstNode(AST_PARASET, attr.second->clone());
|
||||
cell_arg->str = RTLIL::escape_id(attr.first.str().substr(strlen("\\via_celltype_defparam_")));
|
||||
cell_arg->str = RTLIL::escape_id(attr.first.substr(strlen("\\via_celltype_defparam_")));
|
||||
cell->children.push_back(cell_arg);
|
||||
}
|
||||
|
||||
|
|
@ -2793,13 +2793,13 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
|
|||
std::getline(f, line);
|
||||
|
||||
for (int i = 0; i < GetSize(line); i++) {
|
||||
if (in_comment && line.substr(i, 2) == "*/") {
|
||||
if (in_comment && line.compare(i, 2, "*/") == 0) {
|
||||
line[i] = ' ';
|
||||
line[i+1] = ' ';
|
||||
in_comment = false;
|
||||
continue;
|
||||
}
|
||||
if (!in_comment && line.substr(i, 2) == "/*")
|
||||
if (!in_comment && line.compare(i, 2, "/*") == 0)
|
||||
in_comment = true;
|
||||
if (in_comment)
|
||||
line[i] = ' ';
|
||||
|
|
@ -2808,7 +2808,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
|
|||
while (1)
|
||||
{
|
||||
token = next_token(line, " \t\r\n");
|
||||
if (token.empty() || token.substr(0, 2) == "//")
|
||||
if (token.empty() || token.compare(0, 2, "//") == 0)
|
||||
break;
|
||||
|
||||
if (token[0] == '@') {
|
||||
|
|
@ -3439,19 +3439,11 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
|
|||
{
|
||||
std::map<std::string, AstNode*> backup_scope;
|
||||
std::map<std::string, AstNode::varinfo_t> variables;
|
||||
bool delete_temp_block = false;
|
||||
AstNode *block = NULL;
|
||||
AstNode *block = new AstNode(AST_BLOCK);
|
||||
|
||||
size_t argidx = 0;
|
||||
for (auto child : children)
|
||||
{
|
||||
if (child->type == AST_BLOCK)
|
||||
{
|
||||
log_assert(block == NULL);
|
||||
block = child;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (child->type == AST_WIRE)
|
||||
{
|
||||
while (child->simplify(true, false, false, 1, -1, false, true)) { }
|
||||
|
|
@ -3468,13 +3460,9 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
|
|||
continue;
|
||||
}
|
||||
|
||||
log_assert(block == NULL);
|
||||
delete_temp_block = true;
|
||||
block = new AstNode(AST_BLOCK);
|
||||
block->children.push_back(child->clone());
|
||||
}
|
||||
|
||||
log_assert(block != NULL);
|
||||
log_assert(variables.count(str) != 0);
|
||||
|
||||
while (!block->children.empty())
|
||||
|
|
@ -3642,8 +3630,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
|
|||
log_abort();
|
||||
}
|
||||
|
||||
if (delete_temp_block)
|
||||
delete block;
|
||||
delete block;
|
||||
|
||||
for (auto &it : backup_scope)
|
||||
if (it.second == NULL)
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ failed:
|
|||
return std::pair<RTLIL::IdString, int>("\\" + name, 0);
|
||||
}
|
||||
|
||||
void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bool run_clean, bool sop_mode, bool wideports)
|
||||
void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool run_clean, bool sop_mode, bool wideports)
|
||||
{
|
||||
RTLIL::Module *module = nullptr;
|
||||
RTLIL::Const *lutptr = NULL;
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
extern void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name,
|
||||
extern void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name,
|
||||
bool run_clean = false, bool sop_mode = false, bool wideports = false);
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ struct JsonNode
|
|||
{
|
||||
char type; // S=String, N=Number, A=Array, D=Dict
|
||||
string data_string;
|
||||
int data_number;
|
||||
int64_t data_number;
|
||||
vector<JsonNode*> data_array;
|
||||
dict<string, JsonNode*> data_dict;
|
||||
vector<string> data_dict_keys;
|
||||
|
|
@ -206,6 +206,38 @@ struct JsonNode
|
|||
}
|
||||
};
|
||||
|
||||
Const json_parse_attr_param_value(JsonNode *node)
|
||||
{
|
||||
Const value;
|
||||
|
||||
if (node->type == 'S') {
|
||||
string &s = node->data_string;
|
||||
size_t cursor = s.find_first_not_of("01xz");
|
||||
if (cursor == string::npos) {
|
||||
value = Const::from_string(s);
|
||||
} else if (s.find_first_not_of(' ', cursor) == string::npos) {
|
||||
value = Const(s.substr(0, GetSize(s)-1));
|
||||
} else {
|
||||
value = Const(s);
|
||||
}
|
||||
} else
|
||||
if (node->type == 'N') {
|
||||
value = Const(node->data_number, 32);
|
||||
if (node->data_number < 0)
|
||||
value.flags |= RTLIL::CONST_FLAG_SIGNED;
|
||||
} else
|
||||
if (node->type == 'A') {
|
||||
log_error("JSON attribute or parameter value is an array.\n");
|
||||
} else
|
||||
if (node->type == 'D') {
|
||||
log_error("JSON attribute or parameter value is a dict.\n");
|
||||
} else {
|
||||
log_abort();
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
void json_parse_attr_param(dict<IdString, Const> &results, JsonNode *node)
|
||||
{
|
||||
if (node->type != 'D')
|
||||
|
|
@ -214,28 +246,7 @@ void json_parse_attr_param(dict<IdString, Const> &results, JsonNode *node)
|
|||
for (auto it : node->data_dict)
|
||||
{
|
||||
IdString key = RTLIL::escape_id(it.first.c_str());
|
||||
JsonNode *value_node = it.second;
|
||||
Const value;
|
||||
|
||||
if (value_node->type == 'S') {
|
||||
string &s = value_node->data_string;
|
||||
if (s.find_first_not_of("01xz") == string::npos)
|
||||
value = Const::from_string(s);
|
||||
else
|
||||
value = Const(s);
|
||||
} else
|
||||
if (value_node->type == 'N') {
|
||||
value = Const(value_node->data_number, 32);
|
||||
} else
|
||||
if (value_node->type == 'A') {
|
||||
log_error("JSON attribute or parameter value is an array.\n");
|
||||
} else
|
||||
if (value_node->type == 'D') {
|
||||
log_error("JSON attribute or parameter value is a dict.\n");
|
||||
} else {
|
||||
log_abort();
|
||||
}
|
||||
|
||||
Const value = json_parse_attr_param_value(it.second);
|
||||
results[key] = value;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -551,7 +551,7 @@ struct LibertyFrontend : public Frontend {
|
|||
if (design->has(cell_name)) {
|
||||
Module *existing_mod = design->module(cell_name);
|
||||
if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
|
||||
log_error("Re-definition of of cell/module %s!\n", log_id(cell_name));
|
||||
log_error("Re-definition of cell/module %s!\n", log_id(cell_name));
|
||||
} else if (flag_nooverwrite) {
|
||||
log("Ignoring re-definition of module %s.\n", log_id(cell_name));
|
||||
continue;
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/sigtools.h"
|
||||
#include "kernel/celltypes.h"
|
||||
#include "kernel/log.h"
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
|
|
@ -111,9 +112,10 @@ string get_full_netlist_name(Netlist *nl)
|
|||
|
||||
// ==================================================================
|
||||
|
||||
VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover) :
|
||||
VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit) :
|
||||
mode_gates(mode_gates), mode_keep(mode_keep), mode_nosva(mode_nosva),
|
||||
mode_names(mode_names), mode_verific(mode_verific), mode_autocover(mode_autocover)
|
||||
mode_names(mode_names), mode_verific(mode_verific), mode_autocover(mode_autocover),
|
||||
mode_fullinit(mode_fullinit)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -1454,6 +1456,50 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
|
|||
|
||||
merge_past_ffs(past_ffs);
|
||||
}
|
||||
|
||||
if (!mode_fullinit)
|
||||
{
|
||||
pool<SigBit> non_ff_bits;
|
||||
CellTypes ff_types;
|
||||
|
||||
ff_types.setup_internals_ff();
|
||||
ff_types.setup_stdcells_mem();
|
||||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (ff_types.cell_known(cell->type))
|
||||
continue;
|
||||
|
||||
for (auto conn : cell->connections())
|
||||
{
|
||||
if (!cell->output(conn.first))
|
||||
continue;
|
||||
|
||||
for (auto bit : conn.second)
|
||||
if (bit.wire != nullptr)
|
||||
non_ff_bits.insert(bit);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto wire : module->wires())
|
||||
{
|
||||
if (!wire->attributes.count("\\init"))
|
||||
continue;
|
||||
|
||||
Const &initval = wire->attributes.at("\\init");
|
||||
for (int i = 0; i < GetSize(initval); i++)
|
||||
{
|
||||
if (initval[i] != State::S0 && initval[i] != State::S1)
|
||||
continue;
|
||||
|
||||
if (non_ff_bits.count(SigBit(wire, i)))
|
||||
initval[i] = State::Sx;
|
||||
}
|
||||
|
||||
if (initval.is_fully_undef())
|
||||
wire->attributes.erase("\\init");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// ==================================================================
|
||||
|
|
@ -1829,7 +1875,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
|
|||
while (!nl_todo.empty()) {
|
||||
Netlist *nl = *nl_todo.begin();
|
||||
if (nl_done.count(nl) == 0) {
|
||||
VerificImporter importer(false, false, false, false, false, false);
|
||||
VerificImporter importer(false, false, false, false, false, false, false);
|
||||
importer.import_netlist(design, nl, nl_todo);
|
||||
}
|
||||
nl_todo.erase(nl);
|
||||
|
|
@ -1952,6 +1998,9 @@ struct VerificPass : public Pass {
|
|||
log(" -autocover\n");
|
||||
log(" Generate automatic cover statements for all asserts\n");
|
||||
log("\n");
|
||||
log(" -fullinit\n");
|
||||
log(" Keep all register initializations, even those for non-FF registers.\n");
|
||||
log("\n");
|
||||
log(" -chparam name value \n");
|
||||
log(" Elaborate the specified top modules (all modules when -all given) using\n");
|
||||
log(" this parameter value. Modules on which this parameter does not exist will\n");
|
||||
|
|
@ -2140,7 +2189,7 @@ struct VerificPass : public Pass {
|
|||
veri_file::DefineMacro("VERIFIC");
|
||||
veri_file::DefineMacro(args[argidx] == "-formal" ? "FORMAL" : "SYNTHESIS");
|
||||
|
||||
for (argidx++; argidx < GetSize(args) && GetSize(args[argidx]) >= 2 && args[argidx].substr(0, 2) == "-D"; argidx++) {
|
||||
for (argidx++; argidx < GetSize(args) && GetSize(args[argidx]) >= 2 && args[argidx].compare(0, 2, "-D") == 0; argidx++) {
|
||||
std::string name = args[argidx].substr(2);
|
||||
if (args[argidx] == "-D") {
|
||||
if (++argidx >= GetSize(args))
|
||||
|
|
@ -2213,7 +2262,7 @@ struct VerificPass : public Pass {
|
|||
std::set<Netlist*> nl_todo, nl_done;
|
||||
bool mode_all = false, mode_gates = false, mode_keep = false;
|
||||
bool mode_nosva = false, mode_names = false, mode_verific = false;
|
||||
bool mode_autocover = false;
|
||||
bool mode_autocover = false, mode_fullinit = false;
|
||||
bool flatten = false, extnets = false;
|
||||
string dumpfile;
|
||||
Map parameters(STRING_HASH);
|
||||
|
|
@ -2255,6 +2304,10 @@ struct VerificPass : public Pass {
|
|||
mode_autocover = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-fullinit") {
|
||||
mode_fullinit = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-chparam" && argidx+2 < GetSize(args)) {
|
||||
const std::string &key = args[++argidx];
|
||||
const std::string &value = args[++argidx];
|
||||
|
|
@ -2283,7 +2336,7 @@ struct VerificPass : public Pass {
|
|||
break;
|
||||
}
|
||||
|
||||
if (argidx > GetSize(args) && args[argidx].substr(0, 1) == "-")
|
||||
if (argidx > GetSize(args) && args[argidx].compare(0, 1, "-") == 0)
|
||||
cmd_error(args, argidx, "unknown option");
|
||||
|
||||
if (mode_all)
|
||||
|
|
@ -2378,7 +2431,7 @@ struct VerificPass : public Pass {
|
|||
Netlist *nl = *nl_todo.begin();
|
||||
if (nl_done.count(nl) == 0) {
|
||||
VerificImporter importer(mode_gates, mode_keep, mode_nosva,
|
||||
mode_names, mode_verific, mode_autocover);
|
||||
mode_names, mode_verific, mode_autocover, mode_fullinit);
|
||||
importer.import_netlist(design, nl, nl_todo);
|
||||
}
|
||||
nl_todo.erase(nl);
|
||||
|
|
@ -2484,7 +2537,7 @@ struct ReadPass : public Pass {
|
|||
args[0] = "verific";
|
||||
} else {
|
||||
args[0] = "read_verilog";
|
||||
args.erase(args.begin()+1, args.begin()+2);
|
||||
args[1] = "-defer";
|
||||
}
|
||||
Pass::call(design, args);
|
||||
return;
|
||||
|
|
@ -2498,6 +2551,7 @@ struct ReadPass : public Pass {
|
|||
if (args[1] == "-formal")
|
||||
args.insert(args.begin()+1, std::string());
|
||||
args[1] = "-sv";
|
||||
args.insert(args.begin()+1, "-defer");
|
||||
}
|
||||
Pass::call(design, args);
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -72,9 +72,9 @@ struct VerificImporter
|
|||
pool<Verific::Net*, hash_ptr_ops> any_all_nets;
|
||||
|
||||
bool mode_gates, mode_keep, mode_nosva, mode_names, mode_verific;
|
||||
bool mode_autocover;
|
||||
bool mode_autocover, mode_fullinit;
|
||||
|
||||
VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover);
|
||||
VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit);
|
||||
|
||||
RTLIL::SigBit net_map_at(Verific::Net *net);
|
||||
|
||||
|
|
|
|||
|
|
@ -357,7 +357,7 @@ struct SvaFsm
|
|||
for (int i = 0; i < GetSize(nodes); i++)
|
||||
{
|
||||
if (next_state_sig[i] != State::S0) {
|
||||
clocking.addDff(NEW_ID, next_state_sig[i], state_wire[i], Const(0, 1));
|
||||
clocking.addDff(NEW_ID, next_state_sig[i], state_wire[i], State::S0);
|
||||
} else {
|
||||
module->connect(state_wire[i], State::S0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -99,7 +99,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
|
|||
|
||||
if (base == 10) {
|
||||
while (!digits.empty())
|
||||
data.push_back(my_decimal_div_by_two(digits) ? RTLIL::S1 : RTLIL::S0);
|
||||
data.push_back(my_decimal_div_by_two(digits) ? State::S1 : State::S0);
|
||||
} else {
|
||||
int bits_per_digit = my_ilog2(base-1);
|
||||
for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) {
|
||||
|
|
@ -115,17 +115,17 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
|
|||
else if (*it == 0xf2)
|
||||
data.push_back(RTLIL::Sa);
|
||||
else
|
||||
data.push_back((*it & bitmask) ? RTLIL::S1 : RTLIL::S0);
|
||||
data.push_back((*it & bitmask) ? State::S1 : State::S0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int len = GetSize(data);
|
||||
RTLIL::State msb = data.empty() ? RTLIL::S0 : data.back();
|
||||
RTLIL::State msb = data.empty() ? State::S0 : data.back();
|
||||
|
||||
if (len_in_bits < 0) {
|
||||
if (len < 32)
|
||||
data.resize(32, msb == RTLIL::S0 || msb == RTLIL::S1 ? RTLIL::S0 : msb);
|
||||
data.resize(32, msb == State::S0 || msb == State::S1 ? RTLIL::S0 : msb);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -133,11 +133,11 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
|
|||
log_file_error(current_filename, get_line_num(), "Unsized constant must have width of 1 bit, but have %d bits!\n", len);
|
||||
|
||||
for (len = len - 1; len >= 0; len--)
|
||||
if (data[len] == RTLIL::S1)
|
||||
if (data[len] == State::S1)
|
||||
break;
|
||||
if (msb == RTLIL::S0 || msb == RTLIL::S1) {
|
||||
if (msb == State::S0 || msb == State::S1) {
|
||||
len += 1;
|
||||
data.resize(len_in_bits, RTLIL::S0);
|
||||
data.resize(len_in_bits, State::S0);
|
||||
} else {
|
||||
len += 2;
|
||||
data.resize(len_in_bits, msb);
|
||||
|
|
@ -169,7 +169,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
|
|||
for (int i = 0; i < len; i++) {
|
||||
unsigned char ch = str[len - i];
|
||||
for (int j = 0; j < 8; j++) {
|
||||
data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
|
||||
data.push_back((ch & 1) ? State::S1 : State::S0);
|
||||
ch = ch >> 1;
|
||||
}
|
||||
}
|
||||
|
|
@ -190,8 +190,8 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
|
|||
if (*endptr == 0) {
|
||||
std::vector<RTLIL::State> data;
|
||||
my_strtobin(data, str, -1, 10, case_type, false);
|
||||
if (data.back() == RTLIL::S1)
|
||||
data.push_back(RTLIL::S0);
|
||||
if (data.back() == State::S1)
|
||||
data.push_back(State::S0);
|
||||
return AstNode::mkconst_bits(data, true);
|
||||
}
|
||||
|
||||
|
|
@ -237,8 +237,8 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
|
|||
}
|
||||
}
|
||||
if (len_in_bits < 0) {
|
||||
if (is_signed && data.back() == RTLIL::S1)
|
||||
data.push_back(RTLIL::S0);
|
||||
if (is_signed && data.back() == State::S1)
|
||||
data.push_back(State::S0);
|
||||
}
|
||||
return AstNode::mkconst_bits(data, is_signed, is_unsized);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -70,6 +70,9 @@ YOSYS_NAMESPACE_END
|
|||
#define YY_INPUT(buf,result,max_size) \
|
||||
result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
|
||||
|
||||
#undef YY_BUF_SIZE
|
||||
#define YY_BUF_SIZE 65536
|
||||
|
||||
%}
|
||||
|
||||
%option yylineno
|
||||
|
|
|
|||
|
|
@ -274,7 +274,7 @@ hierarchical_id:
|
|||
$$ = $1;
|
||||
} |
|
||||
hierarchical_id TOK_PACKAGESEP TOK_ID {
|
||||
if ($3->substr(0, 1) == "\\")
|
||||
if ($3->compare(0, 1, "\\") == 0)
|
||||
*$1 += "::" + $3->substr(1);
|
||||
else
|
||||
*$1 += "::" + *$3;
|
||||
|
|
@ -282,7 +282,7 @@ hierarchical_id:
|
|||
$$ = $1;
|
||||
} |
|
||||
hierarchical_id '.' TOK_ID {
|
||||
if ($3->substr(0, 1) == "\\")
|
||||
if ($3->compare(0, 1, "\\") == 0)
|
||||
*$1 += "." + $3->substr(1);
|
||||
else
|
||||
*$1 += "." + *$3;
|
||||
|
|
@ -2184,7 +2184,7 @@ basic_expr:
|
|||
$$ = $1;
|
||||
} |
|
||||
'(' expr ')' TOK_CONSTVAL {
|
||||
if ($4->substr(0, 1) != "'")
|
||||
if ($4->compare(0, 1, "'") != 0)
|
||||
frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
|
||||
AstNode *bits = $2;
|
||||
AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
|
||||
|
|
@ -2194,7 +2194,7 @@ basic_expr:
|
|||
delete $4;
|
||||
} |
|
||||
hierarchical_id TOK_CONSTVAL {
|
||||
if ($2->substr(0, 1) != "'")
|
||||
if ($2->compare(0, 1, "'") != 0)
|
||||
frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
|
||||
AstNode *bits = new AstNode(AST_IDENTIFIER);
|
||||
bits->str = *$1;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue