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Author SHA1 Message Date
Eddie Hung
07e50b9c25 Only pack registers if {A,B,P}REG = 0, do not pack $dffe 2019-08-08 10:51:19 -07:00
Eddie Hung
7160243874 Move xilinx_dsp to before alumacc 2019-08-08 10:45:56 -07:00
Eddie Hung
911129e3ef Disable $dffe 2019-08-08 10:44:49 -07:00
Eddie Hung
57b2e4b9c1 INMODE is 5 bits 2019-08-08 10:44:35 -07:00
Eddie Hung
13cc106cf7 Fix copy-pasta typo 2019-08-08 10:44:26 -07:00
David Shah
0492b8b541 ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 15:18:59 +01:00
David Shah
cb84ed2326 ecp5: Bring up to date with mul2dsp changes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 15:14:09 +01:00
David Shah
83b2e02723 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-08 11:40:09 +01:00
David Shah
b8cd4ad64a DSP48E1 sim model: add SIMD tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:39:35 +01:00
David Shah
57aeb4cc01 DSP48E1 model: test CE inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:32:43 +01:00
David Shah
d60b3c0dc8 DSP48E1 sim model: fix seq tests and add preadder tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:18:37 +01:00
David Shah
e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah
f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah
f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah
ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
Eddie Hung
fb568ddb4e Fix compile error 2019-08-07 14:31:55 -07:00
Eddie Hung
a206aed977 Run "opt_expr -fine" instead of "wreduce" due to #1213 2019-08-07 13:59:07 -07:00
Eddie Hung
d90b8b081a Do not SigSpec::extract() beyond bounds 2019-08-07 13:58:26 -07:00
Eddie Hung
e3d898dccb Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-07 13:44:08 -07:00
Eddie Hung
cdf9c80134 Do not pack registers if (* keep *) 2019-08-07 12:57:10 -07:00
Eddie Hung
3414ee1e3f
Merge pull request #1248 from YosysHQ/eddie/abc9_speedup 
abc9: speedup by using using "clean" more efficiently
 2019-08-07 12:25:26 -07:00
Eddie Hung
58e512ab70 Add comment 2019-08-07 09:54:27 -07:00
Eddie Hung
f20acbc813 Revert "Add TODO" 
This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
 2019-08-07 09:54:27 -07:00
Eddie Hung
789585a744 Add TODO 2019-08-07 09:54:27 -07:00
Eddie Hung
8a8c1d7857 Compute box_lookup just once 2019-08-07 09:54:27 -07:00
Eddie Hung
03ec8d6551 Run "clean" on mapped_mod in its own design 2019-08-07 09:54:27 -07:00
Eddie Hung
3090da2d98 Run "clean -purge" on holes_module in its own design 2019-08-07 09:54:27 -07:00
David Shah
5545cd3c10
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes 
ecp5: Make cells_sim.v consistent with nextpnr
 2019-08-07 15:35:29 +01:00
David Shah
a36fd8582e ecp5: Make cells_sim.v consistent with nextpnr 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:19:31 +01:00
Clifford Wolf
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add 
wreduce/opt_expr: improve width reduction for $add and $sub cells
 2019-08-07 14:27:35 +02:00
David Shah
fe95807f16 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 13:09:12 +01:00
Clifford Wolf
48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor 
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
 2019-08-07 12:31:32 +02:00
Clifford Wolf
4c49ddf36a
Merge pull request #1249 from mmicko/anlogic_fix 
anlogic : Fix alu mapping
 2019-08-07 12:30:52 +02:00
Clifford Wolf
679bc6507f
Merge pull request #1252 from YosysHQ/clifford/fix1231 
Fix handling of functions/tasks without top-level begin-end block
 2019-08-07 12:14:54 +02:00
Clifford Wolf
c5d56fbe2d
Merge pull request #1253 from YosysHQ/clifford/check 
Be less aggressive with running design->check()
 2019-08-07 12:14:41 +02:00
Clifford Wolf
f1ac998bb4
Merge pull request #1257 from YosysHQ/clifford/cellcosts 
Redesign of cell cost API
 2019-08-07 12:13:50 +02:00
David Shah
607c7fa7e1 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 10:56:32 +01:00
David Shah
dee8f61781
Merge pull request #1241 from YosysHQ/clifford/jsonfix 
Improved JSON attr/param encoding
 2019-08-07 10:40:38 +01:00
Clifford Wolf
338f6765eb Tweak default gate costs, cleanup "stat -tech cmos" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 10:25:51 +02:00
Clifford Wolf
100c377451 Redesign of cell cost API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 01:12:14 +02:00
Eddie Hung
2d1b517b01 Add signed opt_expr tests 2019-08-06 15:40:30 -07:00
Eddie Hung
769c750c22 Add signed test 2019-08-06 15:38:43 -07:00
Eddie Hung
bfc7164af7 Move LSB-trimming functionality from wreduce to opt_expr 2019-08-06 15:25:50 -07:00
Eddie Hung
84f52aee0d Add SigSpec::extract_end() convenience function 2019-08-06 15:25:11 -07:00
Eddie Hung
0b56be8c56 Restore original SigSpec::extract() 2019-08-06 15:24:55 -07:00
Eddie Hung
51b39219cd Move LSB tests from wreduce to opt_expr 2019-08-06 15:24:49 -07:00
Eddie Hung
26cb3e7afc Merge remote-tracking branch 'origin/master' into eddie/wreduce_add 2019-08-06 14:50:00 -07:00
David Shah
8110fb9266
Merge pull request #1232 from YosysHQ/dave/write_gzip 
Add support for writing gzip-compressed files
 2019-08-06 19:05:35 +01:00
David Shah
c43b0c4b49 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 18:47:18 +01:00
Clifford Wolf
95a6582f34 Be less aggressive with running design->check() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 19:21:37 +02:00