28 commits

Author	SHA1	Message	Date
Eddie Hung	4eb5847dbd	Cleanup	2019-08-28 18:10:33 -07:00
Eddie Hung	52c4655de3	No need to replace Q of slice since $shiftx is autoremove-d	2019-08-28 11:06:11 -07:00
Eddie Hung	86b538bd02	More cleanup	2019-08-28 10:11:09 -07:00
Eddie Hung	c4d1bd988b	Do not use default_params dict, hardcode default values, cleanup	2019-08-28 10:06:40 -07:00
Eddie Hung	9172d4a674	Missing close bracket	2019-08-26 21:02:52 -07:00
Eddie Hung	54422c5bb4	Remove leftover header	2019-08-26 17:51:13 -07:00
Eddie Hung	7911143827	Create new $__XILINX_SHREG_ cell for variable length too	2019-08-23 18:15:49 -07:00
Eddie Hung	188b49378a	Create new cell for fixed length SRL	2019-08-23 17:25:30 -07:00
Eddie Hung	c762618783	Fix last_cell.D	2019-08-23 15:08:49 -07:00
Eddie Hung	8ecfd55d5a	Update doc	2019-08-23 14:16:41 -07:00
Eddie Hung	3d7f4aa0c8	Remove (* init *) entry when consumed into SRL	2019-08-23 13:56:01 -07:00
Eddie Hung	5939ffdc07	Forgot to slice	2019-08-23 13:06:59 -07:00
Eddie Hung	18b64609c2	xilinx_srl to use 'slice' features of pmgen for word level	2019-08-23 12:22:06 -07:00
Eddie Hung	6e8fda8bf0	Add doc	2019-08-22 11:52:24 -07:00
Eddie Hung	cabadb85e2	Add copyright	2019-08-22 11:25:19 -07:00
Eddie Hung	74bd190d3b	Remove output_bits	2019-08-22 11:14:59 -07:00
Eddie Hung	231ddbf95c	Forgot to set ud_variable.minlen	2019-08-22 11:02:17 -07:00
Eddie Hung	61639d5387	Do not run xilinx_srl_pm in fixed loop	2019-08-22 10:51:04 -07:00
Eddie Hung	ed7be3e6b6	Add comment	2019-08-21 17:36:38 -07:00
Eddie Hung	15188033da	Add variable length support to xilinx_srl	2019-08-21 17:34:40 -07:00
Eddie Hung	6d76ae4c65	Rename pattern to fixed	2019-08-21 15:46:58 -07:00
Eddie Hung	6fa9e03e4c	xilinx_srl to support FDRE and FDRE_1	2019-08-21 15:35:29 -07:00
Eddie Hung	3c8e8521a6	Fix polarity of EN_POL	2019-08-21 14:42:11 -07:00
Eddie Hung	a980f0d4be	Add CLKPOL == 0	2019-08-21 14:35:40 -07:00
Eddie Hung	1c7d721558	Reject if not minlen from inside pattern matcher	2019-08-21 14:26:24 -07:00
Eddie Hung	5ce0c31d0e	Add init support	2019-08-21 13:05:10 -07:00
Eddie Hung	df53fe12e7	Fix spacing	2019-08-21 12:54:11 -07:00
Eddie Hung	0250712486	Initial progress on xilinx_srl	2019-08-21 12:50:49 -07:00