4265 commits

Author	SHA1	Message	Date
Alain Dargelas	151be52500	Activity clear pass	2024-10-17 11:02:35 -07:00
Alain Dargelas	f6d67ac21e	More comments	2024-10-17 09:33:08 -07:00
Alain Dargelas	389518a8f0	tab issue	2024-10-16 21:37:41 -07:00
Alain Dargelas	516a4be6f8	Correct tab	2024-10-16 21:17:03 -07:00
Alain Dargelas	3f7c392e1a	activity computation	2024-10-16 20:41:26 -07:00
Akash Levy	711e1f3164	Merge branch 'YosysHQ:main' into main	2024-10-16 13:21:03 -07:00
Martin Povišer	9432e972f7	Merge pull request #4626 from povik/select-t-at ... select: Add new `t:@<name>` syntax	2024-10-16 10:18:05 +02:00
Akash Levy	98db6bd2d8	muldiv_c peepopt pass	2024-10-15 05:29:00 -07:00
Martin Povišer	09be0351ce	select: Add new t:@<name> syntax	2024-10-15 12:22:02 +02:00
Akash Levy	469f5a707a	Merge branch 'YosysHQ:main' into main	2024-10-14 11:21:54 -07:00
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Akash Levy	bf4b7ec0ea	Merge branch 'YosysHQ:main' into main	2024-10-11 15:40:49 -07:00
Martin Povišer	a00137c2f6	Merge pull request #4625 from povik/cellmatch-lut ... cellmatch: Size the `lut` attribute	2024-10-11 14:08:55 +02:00
Akash Levy	71d672ebe9	Fix muxadd peepopt	2024-10-10 13:35:14 -07:00
Akash Levy	0ac341acf2	Merge latest and update yosys-slang dep	2024-10-09 15:34:02 -07:00
KrystalDelusion	0be3b7de51	Merge pull request #4635 from YosysHQ/krys/pr_docs_ci ... Remove make docs race conditions (and other docs fixes)	2024-10-08 21:39:30 +13:00
Miodrag Milanovic	f079772ade	Add TODO for missing help messages	2024-10-08 08:47:51 +02:00
Akash Levy	fdc4c54c66	Merge branch 'YosysHQ:main' into main	2024-10-07 07:27:27 -10:00
Martin Povišer	9479d3bd3c	Merge pull request #4637 from YosysHQ/emil/bufnorm-warning ... bufnorm: avoid warning. NFC	2024-10-07 18:01:42 +02:00
Emil J. Tywoniak	a76bcdc58f	bufnorm: avoid remove warning. NFC	2024-10-07 17:58:48 +02:00
Martin Povišer	74e92d10e8	Merge pull request #4593 from povik/aiger2 ... New aiger backend	2024-10-07 16:11:25 +02:00
Martin Povišer	2e587c835f	abc9_exe: Document SC mapping options	2024-10-07 12:03:49 +02:00
Martin Povišer	3b6dcc7bd0	abc9_exe: Remove -genlib option	2024-10-07 12:03:49 +02:00
Martin Povišer	e0a86d5483	abc_new: Start new command for aiger2-based round trip	2024-10-07 12:03:49 +02:00
Martin Povišer	e58a9b6ab6	abc9: Understand ASIC options similar to abc	2024-10-07 12:03:48 +02:00
Akash Levy	654e92e04e	Fix Liberty issue	2024-10-03 04:14:20 -07:00
Akash Levy	dd487ca8a1	Updating Yosys	2024-10-03 01:46:09 -07:00
Akash Levy	03f76bbddd	Remove comments	2024-10-02 16:59:01 -07:00
Akash Levy	dd7e302aaa	Revert wreduce	2024-10-02 03:55:19 -07:00
Martin Povišer	ec42b42bd9	cellmatch: Size the lut attribute	2024-10-02 11:29:54 +02:00
Akash Levy	599cebfca5	Include pmuxtree	2024-09-29 05:31:51 -07:00
Akash Levy	49d948d873	Fix splitfanout: keep original cell, add new cells to driver db to fix net messup	2024-09-29 03:07:07 -07:00
Akash Levy	7f05f0b273	Fix muxadd peepopt to track bitsplit	2024-09-27 02:28:32 -07:00
Akash Levy	b1383a80cf	Make renaming nicer for bmuxmap -pmux	2024-09-27 00:54:05 -07:00
Akash Levy	dbaaf78044	Iterate to new wire	2024-09-24 16:47:35 -07:00
Akash Levy	ebf8783b4b	Fixup parameters	2024-09-24 13:55:09 -07:00
Akash Levy	9193b0e324	Merge branch 'YosysHQ:main' into main	2024-09-23 06:27:58 -07:00
N. Engelhardt	8e1e2b9a39	Merge pull request #4495 from povik/check-avert-costly-detail	2024-09-23 15:19:48 +02:00
Akash Levy	9f44ec8aa1	Merge branch 'YosysHQ:main' into main	2024-09-17 15:24:05 -07:00
Martin Povišer	38de01807e	Mark bufnorm experimental	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	80119386c0	Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	8bb70bac8d	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d027ead4b5	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	f4b7ea5fb3	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	32808a0393	Improvements and fixes to "bufnorm" cmd ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d0b5dfa6ef	Add bufnorm pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Akash Levy	210ec6585f	Merge branch 'YosysHQ:main' into main	2024-09-16 06:59:25 -07:00
Emil J	52382c6544	Merge pull request #4583 from YosysHQ/emil/clock_gate ... clockgate: centralize clock enables out of FFs	2024-09-16 15:41:01 +02:00
Emil J. Tywoniak	f193bcf683	clockgate: help string	2024-09-16 14:20:33 +02:00
Emil J. Tywoniak	be7c93ec6d	clockgate: 1-bit const 0	2024-09-16 13:58:27 +02:00