Eddie Hung
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0391499e46
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Merge remote-tracking branch 'origin/master' into xaig
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2019-04-15 21:56:45 -07:00 |
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Eddie Hung
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dca45c0888
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Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
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2019-04-15 18:39:20 -07:00 |
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Eddie Hung
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b3378745fd
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Revert "Recognise default entry in case even if all cases covered (fix for #931)"
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2019-04-15 17:52:45 -07:00 |
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Eddie Hung
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18a4045858
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Merge pull request #936 from YosysHQ/README-fix-quotes
README: fix some incorrect quoting
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2019-04-15 12:22:05 -07:00 |
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whitequark
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6323e73cc9
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README: fix some incorrect quoting.
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2019-04-15 14:29:46 +00:00 |
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Eddie Hung
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fecafb2207
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Forgot backslashes
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2019-04-12 18:22:44 -07:00 |
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Eddie Hung
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9bfcd80063
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Handle __dummy_o__ and __const[01]__ in read_aiger not abc
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2019-04-12 18:21:16 -07:00 |
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Eddie Hung
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482a60825b
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abc to ignore __dummy_o__ and __const[01]__ when re-integrating
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2019-04-12 18:16:50 -07:00 |
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Eddie Hung
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fe0b421212
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Output __const0__ and __const1__ CIs
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2019-04-12 18:16:25 -07:00 |
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Eddie Hung
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c776db3320
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
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2019-04-12 17:09:24 -07:00 |
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Eddie Hung
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acf3f5694b
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Fix inout handling for -map option
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2019-04-12 17:02:24 -07:00 |
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Eddie Hung
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a16123cc7d
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
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2019-04-12 16:31:12 -07:00 |
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Eddie Hung
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d880f73c79
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Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12 16:30:53 -07:00 |
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Eddie Hung
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88d43a519b
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Use -map instead of -symbols for aiger
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2019-04-12 16:29:14 -07:00 |
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Eddie Hung
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686e772f0b
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ci_bits and co_bits now a list, order is important for ABC
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2019-04-12 16:17:48 -07:00 |
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Eddie Hung
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ada130b459
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Also cope with duplicated CIs
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2019-04-12 16:17:12 -07:00 |
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Eddie Hung
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c748391730
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WIP
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2019-04-12 14:13:11 -07:00 |
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Eddie Hung
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941365b4bb
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Comment out
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2019-04-12 12:29:04 -07:00 |
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Eddie Hung
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04e466d5e4
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Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
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2019-04-12 12:28:37 -07:00 |
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Eddie Hung
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1c6f0cffd9
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Cope with an output having same name as an input (i.e. CO)
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2019-04-12 12:27:07 -07:00 |
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Eddie Hung
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f77da46a87
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Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12 12:21:48 -07:00 |
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Eddie Hung
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db1a5ec6a2
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Merge pull request #928 from litghost/add_xc7_sim_models
Add additional cells sim models for core 7-series primitives.
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2019-04-12 11:52:45 -07:00 |
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Keith Rothman
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1f9235ede5
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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-04-12 09:35:15 -07:00 |
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Clifford Wolf
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9d6586b4e1
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Merge pull request #933 from dh73/master
Fixing issues in CycloneV cell sim
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2019-04-12 14:57:36 +02:00 |
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Clifford Wolf
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48bc203653
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Merge pull request #932 from YosysHQ/eddie/fixdlatch
Recognise default entry in case even if all cases covered (fix for #931)
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2019-04-12 14:57:01 +02:00 |
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Diego
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643ae9bfc5
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Fixing issues in CycloneV cell sim
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2019-04-11 19:59:03 -05:00 |
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Eddie Hung
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7685469ee2
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Add default entry to testcase
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2019-04-11 15:03:40 -07:00 |
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Eddie Hung
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adc6efb584
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Recognise default entry in case even if all cases covered (#931)
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2019-04-11 12:34:51 -07:00 |
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Eddie Hung
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2217d59e29
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Add non-input bits driven by unrecognised cells as ci_bits
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2019-04-10 18:06:33 -07:00 |
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Eddie Hung
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1a49cf29d8
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parse_aiger() to rename all $lut cells after "clean"
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2019-04-10 14:02:23 -07:00 |
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Keith Rothman
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e107ccdde8
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Fix LUT6_2 definition.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-04-09 11:43:19 -07:00 |
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Keith Rothman
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5e0339855f
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Add additional cells sim models for core 7-series primatives.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-04-09 09:01:53 -07:00 |
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Eddie Hung
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0deaccbaae
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Fix a few typos
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2019-04-08 16:46:33 -07:00 |
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Eddie Hung
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12c34136ba
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More space fixing
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2019-04-08 16:40:17 -07:00 |
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Eddie Hung
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36efec01b8
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Fix spacing
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2019-04-08 16:37:22 -07:00 |
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Eddie Hung
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bca3cf6843
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Merge branch 'master' into xaig
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2019-04-08 16:31:59 -07:00 |
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Clifford Wolf
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e194e65358
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Merge pull request #919 from YosysHQ/multiport_transp
memory_bram: Fix multiport make_transp
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2019-04-08 21:14:05 +02:00 |
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David Shah
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2bf3ca6443
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memory_bram: Fix multiport make_transp
Signed-off-by: David Shah <dave@ds0.me>
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2019-04-07 16:56:31 +01:00 |
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Clifford Wolf
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dfb242c905
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Add "read_ilang -lib"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-05 17:31:49 +02:00 |
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Clifford Wolf
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75ca06526a
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Added missing argument checking to "mutate" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-04 18:10:10 +02:00 |
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Eddie Hung
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ef84b434a5
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Merge pull request #913 from smunaut/fix_proc_mux
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
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2019-04-03 06:27:41 -07:00 |
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Sylvain Munaut
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39380c45ba
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proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
last_mux_cell can be NULL ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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2019-04-03 14:50:12 +02:00 |
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Clifford Wolf
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721fa1cbd8
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Merge pull request #912 from YosysHQ/bram_addr_en
memory_bram: Consider read enable for address expansion register
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2019-04-03 10:00:18 +02:00 |
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Clifford Wolf
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3f6554d698
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Merge pull request #910 from ucb-bar/memupdates
Refine memory support to deal with general Verilog memory definitions.
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2019-04-03 09:59:11 +02:00 |
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David Shah
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6acbc016f4
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memory_bram: Consider read enable for address expansion register
Signed-off-by: David Shah <dave@ds0.me>
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2019-04-02 19:47:50 +01:00 |
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Eddie Hung
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aaa2690a56
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Merge pull request #895 from YosysHQ/pmux2shiftx
RFC: Add a pmux-to-shiftx optimisation to proc_mux
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2019-04-02 00:16:14 -07:00 |
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Jim Lawson
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73b87e7807
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Refine memory support to deal with general Verilog memory definitions.
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2019-04-01 15:02:12 -07:00 |
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Clifford Wolf
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22035c20ff
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Merge pull request #907 from YosysHQ/clifford/fix906
Build Verilog parser with -DYYMAXDEPTH=100000
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2019-03-30 00:09:42 +01:00 |
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Clifford Wolf
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584d2030bf
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Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-29 16:32:44 +01:00 |
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Clifford Wolf
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32bd0f22ec
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Merge pull request #901 from trcwm/libertyfixes
Libertyfixes: accept superfluous ; at end of group.
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2019-03-28 09:32:05 +01:00 |
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