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Author SHA1 Message Date
Eddie Hung
0364a5d811 Merge branch 'eddie/fix_retime' into xc7srl 2019-04-05 15:46:18 -07:00
Eddie Hung
9758701574 Move techamp t:$_DFF_?N? to before abc call 2019-04-05 15:39:05 -07:00
Eddie Hung
23a6533e98 Retry 2019-04-05 15:31:54 -07:00
Eddie Hung
3c253818ca "&nf -D 0" fails => use "-D 1" instead 2019-04-05 15:30:19 -07:00
Eddie Hung
8b6085254a Resolve @daveshah1 comment, update synth_xilinx help 2019-04-05 15:15:13 -07:00
Eddie Hung
ff0912c75e synth_xilinx to techmap FFs after abc call, otherwise -retime fails 2019-04-05 14:43:06 -07:00
Eddie Hung
19271bd996 abc -dff now implies "-D 0" otherwise retiming doesn't happen 2019-04-05 14:42:25 -07:00
Eddie Hung
544843da71 techmap inside map_cells stage 2019-04-05 12:55:52 -07:00
Clifford Wolf
dfb242c905 Add "read_ilang -lib" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-05 17:31:49 +02:00
Clifford Wolf
75ca06526a Added missing argument checking to "mutate" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-04 18:10:10 +02:00
Eddie Hung
7b7ddbdba7 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-04 08:13:34 -07:00
Eddie Hung
e3f20b17af Missing techmap entry in help 2019-04-04 08:13:10 -07:00
Eddie Hung
2fb02247a7 Use soft-logic, not LUT3 instantiation 2019-04-04 08:10:40 -07:00
Eddie Hung
572603409c Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-04 07:54:42 -07:00
Eddie Hung
d9cb787391 synth_xilinx to map_cells before map_luts 2019-04-04 07:48:13 -07:00
Eddie Hung
77755b5a66 Cleanup comments 2019-04-04 07:41:40 -07:00
Eddie Hung
736e19f02d t:$dff* -> t:$dff t:$dffe 2019-04-04 07:39:19 -07:00
Eddie Hung
aa693d5723 Remove handling for $pmux, since #895 2019-04-03 08:35:32 -07:00
Eddie Hung
0e2d929cea -nosrl meant when -nobram 2019-04-03 08:28:07 -07:00
Eddie Hung
ff385a5ad0 Remove duplicate STARTUPE2 2019-04-03 08:14:09 -07:00
Eddie Hung
88630cd02c Disable shregmap in synth_xilinx if -retime 2019-04-03 07:14:20 -07:00
Eddie Hung
f7a0434d54 Add changelog entry 2019-04-03 07:05:28 -07:00
Eddie Hung
ef84b434a5
Merge pull request #913 from smunaut/fix_proc_mux 
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
 2019-04-03 06:27:41 -07:00
Sylvain Munaut
39380c45ba proc_mux: Fix crash when trying to optimize non-existant mux to shiftx 
last_mux_cell can be NULL ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-04-03 14:50:12 +02:00
Eddie Hung
d8465590ac Merge remote-tracking branch 'origin/master' into xc7srl 2019-04-03 03:36:11 -07:00
Clifford Wolf
721fa1cbd8
Merge pull request #912 from YosysHQ/bram_addr_en 
memory_bram: Consider read enable for address expansion register
 2019-04-03 10:00:18 +02:00
Clifford Wolf
3f6554d698
Merge pull request #910 from ucb-bar/memupdates 
Refine memory support to deal with general Verilog memory definitions.
 2019-04-03 09:59:11 +02:00
David Shah
6acbc016f4 memory_bram: Consider read enable for address expansion register 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 19:47:50 +01:00
Eddie Hung
aaa2690a56
Merge pull request #895 from YosysHQ/pmux2shiftx 
RFC: Add a pmux-to-shiftx optimisation to proc_mux
 2019-04-02 00:16:14 -07:00
Jim Lawson
73b87e7807 Refine memory support to deal with general Verilog memory definitions. 2019-04-01 15:02:12 -07:00
Clifford Wolf
22035c20ff
Merge pull request #907 from YosysHQ/clifford/fix906 
Build Verilog parser with -DYYMAXDEPTH=100000
 2019-03-30 00:09:42 +01:00
Clifford Wolf
584d2030bf Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-29 16:32:44 +01:00
Clifford Wolf
32bd0f22ec
Merge pull request #901 from trcwm/libertyfixes 
Libertyfixes: accept superfluous ; at end of group.
 2019-03-28 09:32:05 +01:00
Clifford Wolf
662429cc49
Merge pull request #903 from YosysHQ/bram_reset_transp 
memory_bram: Reset make_transp when growing read ports
 2019-03-28 09:30:48 +01:00
David Shah
60594ad40c memory_bram: Reset make_transp when growing read ports 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-27 17:19:14 +00:00
Niels Moseley
263ab60b43 Liberty file parser now accepts superfluous ; 2019-03-27 15:17:58 +01:00
Niels Moseley
ee130f67cd Liberty file parser now accepts superfluous ; 2019-03-27 15:16:19 +01:00
Niels Moseley
487cb45b87 Liberty file parser now accepts superfluous ; 2019-03-27 15:15:53 +01:00
Clifford Wolf
7682629b79 Add "read -verific" and "read -noverific" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-27 14:03:35 +01:00
Clifford Wolf
2c7fe42ad1 Add "rename -output" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-27 13:47:42 +01:00
Clifford Wolf
d351b7cb99 Improve "rename" help message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-27 13:33:26 +01:00
Clifford Wolf
38b3fbd3f0 Add "cutpoint -undef" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-26 16:01:14 +01:00
Clifford Wolf
d0b9b1bece Add "hdlname" attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-26 14:52:48 +01:00
Clifford Wolf
c863796e9f Fix "verific -extnets" for more complex situations 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-26 14:17:46 +01:00
Eddie Hung
f9fb05cf66 synth_xilinx to use shregmap with -minlen 3 2019-03-25 13:18:55 -07:00
Eddie Hung
6b90d3cf6c Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-25 13:17:22 -07:00
Clifford Wolf
ddc1a4488e Add "cutpoint" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-25 19:49:00 +01:00
Eddie Hung
b7a3d35c6b Create one $shiftx per bit in width 2019-03-25 11:16:56 -07:00
Clifford Wolf
9ec50ca7b9
Merge pull request #896 from YosysHQ/transp_fixes 
memory_bram: Fix multiclock make_transp
 2019-03-25 14:55:16 +01:00
Clifford Wolf
2bb9632944
Merge pull request #897 from trcwm/libertyfixes 
Liberty parser: Accept ranges [A:B], and ignore missing ';'.
 2019-03-25 14:47:33 +01:00