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Code Activity
11462 commits 122 branches 59 tags 72 MiB
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1295 commits

Author SHA1 Message Date
Aki Van Ness
1f1a403cce pass jny: flipped the defaults for the inclusion of various bits of metadata 2022-04-08 08:05:15 +02:00
Aki Van Ness
6053856f91 pass jny: ensured the cell collection is cleared between modules 2022-04-08 08:05:15 +02:00
Aki Van Ness
5a016713cc pass jny: fixed missing quotes around the type value for the cell sort 2022-04-08 08:05:15 +02:00
Aki Van Ness
2e792857e9 pass jny: fixed the backslash escape for strings 2022-04-08 08:05:15 +02:00
Aki Van Ness
cae5ea8337 pass jny: removed the invalid json escapes 2022-04-08 08:05:15 +02:00
Aki Van Ness
dccc89e8b3 pass jny: added some todo comments about things that need to be done before a proper merge, but it should be enough for the PoC at the moment 2022-04-08 08:05:15 +02:00
Aki Van Ness
1be9bef28b pass jny: changed the constructor initializers to use parens rather than curly-braces to hopefully make GCC 4.8 happy 2022-04-08 08:05:15 +02:00
Aki Van Ness
43b2fc5566 pass jny: fixed the string escape method to be less jank and more proper 2022-04-08 08:05:15 +02:00
Aki Van Ness
52ea944012 pass jny: fixed the signed output for param value output 2022-04-08 08:05:15 +02:00
Aki Van Ness
58e2870261 pass jny: added connection output 2022-04-08 08:05:15 +02:00
Aki Van Ness
167206f2f5 pass jny: added filter options for including connections, attributes, and properties 2022-04-08 08:05:15 +02:00
Aki Van Ness
587f31b9a3 pass jny: large chunk of refactoring to make the JSON output more pretty and the internals less of a spaghetti nightmare 2022-04-08 08:05:15 +02:00
Aki Van Ness
0e20619189 metadata -> jny: migrated to the proper name for the pass 2022-04-08 08:05:15 +02:00
Aki Van Ness
bdf14557ca pass metadata: added the machinery to write param and attributes 2022-04-08 08:05:15 +02:00
Aki Van Ness
1876ed21e7 pass metadata: removed superfluous stringf calls 2022-04-08 08:05:15 +02:00
Aki Van Ness
ca03fbdc6d pass metadata: some more rough work on dumping the parameters and attributes 2022-04-08 08:05:15 +02:00
Aki Van Ness
6a90b42c48 pass metadata: fixed the MetadataWriter object initializer so GCC 4.8 is happy 2022-04-08 08:05:15 +02:00
Aki Van Ness
7a275567df pass metadata: added the output of parameters, 
it's kinda dumb at the moment and needs parsing based on type but it's a start
 2022-04-08 08:05:15 +02:00
Aki Van Ness
d8b85e1247 pass metadata: fixed some of the output formatting 2022-04-08 08:05:15 +02:00
Aki Van Ness
f6bb238051 pass metadata: initial commit of the metadata pass for exporting design metadata for yosys assisted tooling 2022-04-08 08:05:15 +02:00
Jannis Harder
8b15f3a548 smtbmc: fix bmc with no assertions 
this was broken by the `--keep-going` changes
 2022-03-29 20:41:50 +02:00
Jannis Harder
8cc8c5efde
Merge pull request #3253 from jix/smtbmc-nodeepcopy 
smtbmc: Avoid unnecessary deep copies during unrolling
 2022-03-28 16:59:26 +02:00
Jannis Harder
17e2a3048c
Merge pull request #3247 from jix/smtbmc-keepgoing 
smtbmc `--keep-going`
 2022-03-28 16:58:41 +02:00
Jannis Harder
d25daa6203 smtbmc: Avoid unnecessary deep copies during unrolling 2022-03-28 13:03:48 +02:00
Miodrag Milanovic
4fd8b38d7a Add -no-startoffset option to write_aiger 2022-03-25 08:44:45 +01:00
Jannis Harder
5e4d804e53 yosys-smtbmc: Option to keep going after failed assertions in BMC mode 2022-03-24 16:01:14 +01:00
Jannis Harder
e43ebf8527 yosys-smtbmc: Fix typo in help text, remove trailing whitespace 2022-03-24 16:01:14 +01:00
N. Engelhardt
a7ee01065a ignore # comment lines 2022-03-24 10:19:17 +01:00
Miodrag Milanović
2f44683f4f
Merge pull request #3226 from YosysHQ/micko/btor2witness 
Sim support for btor2 witness files
 2022-03-11 15:29:34 +01:00
Claire Xenia Wolf
d340f302f6 Fix handling of some formal cells in btor back-end 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 14:21:12 +01:00
Miodrag Milanovic
ebe2ee431e handle state names of $anyconst and $anyseq 2022-03-11 14:04:02 +01:00
Miodrag Milanović
4ccc2adbda
Merge pull request #3210 from rqou/json-signed 
json: Add help message for `signed` field
 2022-03-07 09:41:25 +01:00
Miodrag Milanović
a95e5d505b
Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_id 
add argument for printing cell names in yosys-smtbmc
 2022-03-04 16:39:12 +01:00
Miodrag Milanović
c3124023e4
Merge pull request #3207 from nakengelhardt/json_escape_quotes 
fix handling of escaped chars in json backend and frontend (mostly)
 2022-03-04 13:57:32 +01:00
N. Engelhardt
dc739362c7 print cell name for properties in yosys-smtbmc 2022-02-22 17:00:10 +01:00
R
2d3a337795 json: Add help message for signed field 2022-02-21 21:59:25 -08:00
N. Engelhardt
8fd1b06249 fix handling of escaped chars in json backend and frontend 2022-02-18 17:13:09 +01:00
Claire Xenia Wolf
30eb7f8665 Add a bit of flexibilty re trace length when processing aiger witnesses in smtbmc.py 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-11 17:24:49 +01:00
Marcelina Kościelnicka
56e7791760 verilog backend: Emit a wire for ports as well. 
Fixes #3177.
 2022-01-31 01:08:41 +01:00
Marcelina Kościelnicka
93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Catherine
fc049e84a9 cxxrtl: don't reset elided wires with \init attribute. 2021-12-25 01:06:10 +00:00
Catherine
7f2ea7d222 cxxrtl: demote wires not inlinable only in debug_eval to locals. 
Fixes #3112.

Co-authored-by: Irides <irides@irides.network>
 2021-12-15 09:14:33 +00:00
Marcelina Kościelnicka
0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. 
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
 2021-12-12 19:56:50 +01:00
Catherine
bdc6ba019c
Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2 
cxxrtl: preserve interior memory pointers across reset
 2021-12-12 01:23:03 +00:00
Marcelina Kościelnicka
d019b4e681 rtlil: Dump empty connections when whole module is selected. 
Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires.  This makes debugging rather confusing.
 2021-12-12 01:22:06 +01:00
Catherine
55c9fb3b18 cxxrtl: preserve interior memory pointers across reset. 
Before this commit, values, wires, and memories with an initializer
were value-initialized in emitted C++ code. After this commit, all
values, wires, and memories are default-initialized, and the default
constructor of generated modules calls the reset() method, which
assigns the members that have an initializer.
 2021-12-11 16:40:06 +00:00
whitequark
7c9e498662 cxxrtl: use unique_ptr<value<>[]> to store memory contents. 
This makes the depth properly immutable.
 2021-12-11 14:52:37 +00:00
whitequark
86f2804dc3 write_verilog: dump zero width sigspecs correctly. 
Before this commit, zero width sigspecs were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

PR #1203 has addressed this issue before, but in an incomplete way.
 2021-12-11 12:01:52 +00:00
Lofty
77327b2544 sta: very crude static timing analysis pass 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2021-11-25 17:20:27 +01:00
Miodrag Milanovic
c081c683a4 Give initial wire unique ID, fixes #2914 2021-11-17 12:19:06 +01:00