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https://github.com/YosysHQ/yosys
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Add $bmux and $demux cells.
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parent
db33b1e535
commit
93508d58da
25 changed files with 694 additions and 49 deletions
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@ -1399,6 +1399,11 @@ struct BtorBackend : public Backend {
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log_header(design, "Executing BTOR backend.\n");
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log_push();
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Pass::call(design, "bmuxmap");
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Pass::call(design, "demuxmap");
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log_pop();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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@ -457,6 +457,42 @@ struct value : public expr_base<value<Bits>> {
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return shr<AmountBits, /*Signed=*/true>(amount);
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}
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template<size_t ResultBits, size_t SelBits>
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value<ResultBits> bmux(const value<SelBits> &sel) const {
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static_assert(ResultBits << SelBits == Bits, "invalid sizes used in bmux()");
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size_t amount = sel.data[0] * ResultBits;
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size_t shift_chunks = amount / chunk::bits;
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size_t shift_bits = amount % chunk::bits;
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value<ResultBits> result;
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chunk::type carry = 0;
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if (ResultBits % chunk::bits + shift_bits > chunk::bits)
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carry = data[result.chunks + shift_chunks] << (chunk::bits - shift_bits);
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for (size_t n = 0; n < result.chunks; n++) {
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result.data[result.chunks - 1 - n] = carry | (data[result.chunks + shift_chunks - 1 - n] >> shift_bits);
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carry = (shift_bits == 0) ? 0
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: data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);
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}
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return result;
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}
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template<size_t ResultBits, size_t SelBits>
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value<ResultBits> demux(const value<SelBits> &sel) const {
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static_assert(Bits << SelBits == ResultBits, "invalid sizes used in demux()");
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size_t amount = sel.data[0] * Bits;
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size_t shift_chunks = amount / chunk::bits;
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size_t shift_bits = amount % chunk::bits;
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value<ResultBits> result;
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chunk::type carry = 0;
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for (size_t n = 0; n < chunks; n++) {
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result.data[shift_chunks + n] = (data[n] << shift_bits) | carry;
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carry = (shift_bits == 0) ? 0
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: data[n] >> (chunk::bits - shift_bits);
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}
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if (Bits % chunk::bits + shift_bits > chunk::bits)
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result.data[shift_chunks + chunks] = carry;
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return result;
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}
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size_t ctpop() const {
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size_t count = 0;
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for (size_t n = 0; n < chunks; n++) {
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@ -198,7 +198,7 @@ bool is_extending_cell(RTLIL::IdString type)
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bool is_inlinable_cell(RTLIL::IdString type)
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{
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return is_unary_cell(type) || is_binary_cell(type) || type.in(
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ID($mux), ID($concat), ID($slice), ID($pmux));
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ID($mux), ID($concat), ID($slice), ID($pmux), ID($bmux), ID($demux));
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}
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bool is_ff_cell(RTLIL::IdString type)
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@ -1154,6 +1154,22 @@ struct CxxrtlWorker {
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for (int part = 0; part < s_width; part++) {
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f << ")";
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}
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// Big muxes
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} else if (cell->type == ID($bmux)) {
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dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
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f << ".bmux<";
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f << cell->getParam(ID::WIDTH).as_int();
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f << ">(";
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dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
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f << ").val()";
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// Demuxes
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} else if (cell->type == ID($demux)) {
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dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
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f << ".demux<";
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f << GetSize(cell->getPort(ID::Y));
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f << ">(";
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dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
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f << ").val()";
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// Concats
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} else if (cell->type == ID($concat)) {
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dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
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@ -1188,6 +1188,8 @@ struct FirrtlBackend : public Backend {
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log("Write a FIRRTL netlist of the current design.\n");
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log("The following commands are executed by this command:\n");
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log(" pmuxtree\n");
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log(" bmuxmap\n");
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log(" demuxmap\n");
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log("\n");
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
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@ -1210,7 +1212,9 @@ struct FirrtlBackend : public Backend {
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log_header(design, "Executing FIRRTL backend.\n");
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log_push();
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Pass::call(design, stringf("pmuxtree"));
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Pass::call(design, "pmuxtree");
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Pass::call(design, "bmuxmap");
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Pass::call(design, "demuxmap");
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namecache.clear();
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autoid_counter = 0;
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@ -1531,6 +1531,11 @@ struct Smt2Backend : public Backend {
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log_header(design, "Executing SMT2 backend.\n");
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log_push();
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Pass::call(design, "bmuxmap");
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Pass::call(design, "demuxmap");
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log_pop();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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@ -741,6 +741,11 @@ struct SmvBackend : public Backend {
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log_header(design, "Executing SMV backend.\n");
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log_push();
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Pass::call(design, "bmuxmap");
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Pass::call(design, "demuxmap");
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log_pop();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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@ -2300,7 +2300,11 @@ struct VerilogBackend : public Backend {
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extmem_prefix = filename.substr(0, filename.rfind('.'));
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}
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log_push();
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Pass::call(design, "bmuxmap");
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Pass::call(design, "demuxmap");
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Pass::call(design, "clean_zerowidth");
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log_pop();
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design->sort();
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