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Code Activity
2342 commits 124 branches 59 tags 44 MiB
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Author SHA1 Message Date
Mingyu Gao
021b4a2436 Bugfix for cell hash cache option in opt_share. 2015-08-10 13:01:44 -07:00
Clifford Wolf
883e09d8ed Use MEMID as name for $mem cell 2015-08-09 13:35:44 +02:00
Clifford Wolf
3565e89a8b Merge pull request #69 from zeldin/master 
Added iCE40 WARMBOOT cell
 2015-08-07 00:03:39 +02:00
Marcus Comstedt
c9e56bc428 Added iCE40 WARMBOOT cell 2015-08-06 22:58:17 +02:00
Clifford Wolf
6834461f65 Remove some very strange whitespace in btor.cc (by Larry Doolittle) 2015-08-05 22:11:26 +02:00
Clifford Wolf
5dc23975eb Bugfix in SMV back-end for partially unassigned wires 2015-08-05 11:36:26 +02:00
Clifford Wolf
4e4b156e13 Added ENABLE_LIBYOSYS Makefile option 2015-08-04 20:25:26 +02:00
Clifford Wolf
c7fd3fbb68 Added $assert support to SMV back-end 2015-08-04 20:05:37 +02:00
Clifford Wolf
31b555ae72 Added libyosys.so build 2015-08-04 13:22:49 +02:00
Clifford Wolf
c63e5ed7ec Merge pull request #68 from zeldin/master 
Add -noautowire option to verilog frontend
 2015-08-01 12:52:10 +02:00
Marcus Comstedt
c836faae3e Add -noautowire option to verilog frontend 2015-08-01 12:16:54 +02:00
Clifford Wolf
8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf
3860c9a9f2 Fixed flatten $meminit handling 2015-07-30 21:43:41 +02:00
Clifford Wolf
eac0bcd7d3 Improvements in BLIF back-end 2015-07-29 17:06:19 +02:00
Clifford Wolf
4513ff1b85 Fixed nested mem2reg 2015-07-29 16:37:08 +02:00
Clifford Wolf
516e8828f2 Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) 2015-07-27 22:44:01 +02:00
Clifford Wolf
4d0ba9b3b2 Fixed "check" command for inout ports 2015-07-27 09:54:58 +02:00
Clifford Wolf
2a613b1b66 Some cleanups in opt_rmdff 2015-07-25 12:09:57 +02:00
Clifford Wolf
badc5f7eb9 Added "miter -assert" 2015-07-25 12:09:57 +02:00
Clifford Wolf
2397078485 Keep modules with $assume (like $assert) 2015-07-25 12:09:57 +02:00
Clifford Wolf
914ae3401e Improved $adff simplification 2015-07-24 14:12:50 +02:00
Clifford Wolf
c6ca4780e2 iCE40 DFF sim models: init Q regs to 0 2015-07-20 13:05:18 +02:00
Clifford Wolf
ad919ae4e3 Fixed techmap processes error msg 2015-07-18 12:16:27 +02:00
Clifford Wolf
54588a276a Avoid tristate warning for blackbox ice40/cells_sim.v 2015-07-18 11:59:04 +02:00
Clifford Wolf
8393f70538 Some fixes in "select" command 2015-07-16 22:10:26 +02:00
Clifford Wolf
55acc51ad4 Fixed YosysJS.create_worker() usage of this.url_prefix 2015-07-10 13:20:57 +02:00
Clifford Wolf
85aaf08e53 Improved liberty file test case 2015-07-06 17:45:56 +02:00
Clifford Wolf
3049a08912 Updated ABC 2015-07-06 17:45:40 +02:00
Clifford Wolf
d2ff5d9994 Do not collect disabled $memwr cells 2015-07-06 13:28:00 +02:00
Clifford Wolf
c4dde71dca Improved YosysJS WebWorker API 2015-07-04 17:08:44 +02:00
Clifford Wolf
766dd51447 Bugfix in fsm_extract 2015-07-03 18:42:36 +02:00
Clifford Wolf
f0c9a099d2 Added "synth -nofsm" 2015-07-02 15:25:38 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
053058d781 Added opt_const -clkinv 2015-07-01 10:49:21 +02:00
Clifford Wolf
ee9188a5b4 Added logic-loop error handling to freduce 2015-06-30 17:11:46 +02:00
Clifford Wolf
7987f23200 Merge branch 'master' of github.com:cliffordwolf/yosys 2015-06-30 01:49:55 +02:00
Clifford Wolf
77e89399a6 Bugfix in chparam 2015-06-30 01:38:34 +02:00
Clifford Wolf
caa274ada6 Added design->rename(module, new_name) 2015-06-30 01:37:59 +02:00
Clifford Wolf
358e415918 Added YosysJS.create_worker() 2015-06-28 17:47:58 +02:00
Clifford Wolf
df0163cd2b iCE40: set min bram efficiency to 2% 2015-06-20 09:31:19 +02:00
Clifford Wolf
94fbaff58f Using static mem size of 128 MB in emcc build 2015-06-20 08:58:02 +02:00
Clifford Wolf
3123c45415 Added init support to SMV back-end 2015-06-19 16:43:02 +02:00
Clifford Wolf
6c6bf4999e Progress in SMV back-end 2015-06-19 16:26:53 +02:00
Clifford Wolf
8c79765de5 Progress in SMV back-end 2015-06-19 14:08:46 +02:00
Clifford Wolf
8a86162ae9 Progress in SMV back-end 2015-06-18 16:29:11 +02:00
Clifford Wolf
8e84418225 Progress in SMV back-end 2015-06-17 09:56:42 +02:00
Clifford Wolf
99100f367d Added "rename -top new_name" 2015-06-17 09:38:56 +02:00
Clifford Wolf
9f7a5b4ef9 Progress in SMV back-end 2015-06-17 07:24:27 +02:00
Clifford Wolf
b8c5e27006 Progress in SMV back-end 2015-06-16 19:05:26 +02:00
Clifford Wolf
ed128b82d7 Added "synth -nordff -noalumacc" 2015-06-15 17:07:40 +02:00