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Author	SHA1	Message	Date
Clifford Wolf	00e05b1310	Added equiv_struct command	2015-10-21 17:12:35 +02:00
Clifford Wolf	6416dfee93	Improved inout handling in equiv_make	2015-10-21 15:42:50 +02:00
Clifford Wolf	bbcbf739e6	Progress on cell help messages	2015-10-20 16:49:11 +02:00
Clifford Wolf	5d1c0ce7c0	Progress on cell help messages	2015-10-17 02:35:19 +02:00
Clifford Wolf	255bb914ba	Progress in yosys-smtbmc	2015-10-15 15:54:59 +02:00
Clifford Wolf	5308c1e02a	Fixed bug in verilog parser	2015-10-15 15:19:23 +02:00
Clifford Wolf	302166dd59	Improvements in yosys-smtbmc	2015-10-15 15:10:33 +02:00
Clifford Wolf	1d83854d84	Bugfixes in handling of "keep" attribute on wires	2015-10-15 14:57:28 +02:00
Clifford Wolf	5dd3e93e8f	More "yosys-smtbmc -c" fixes	2015-10-14 23:23:25 +02:00
Clifford Wolf	9fd0f87059	Fixed yosys-smtbmc -c	2015-10-14 23:00:46 +02:00
Clifford Wolf	25c1f6e605	Added "prep" command	2015-10-14 22:46:41 +02:00
Clifford Wolf	87adb523aa	Added more cell descriptions	2015-10-14 20:30:59 +02:00
Clifford Wolf	7d3a3a3173	Added first help messages for cell types	2015-10-14 16:27:42 +02:00
Clifford Wolf	3c31572152	Added yosys-smtbmc copyright	2015-10-14 01:31:54 +02:00
Clifford Wolf	d7de0f4bd1	Improvements in yosys-smtbmc	2015-10-14 01:27:55 +02:00
Clifford Wolf	821f1b8534	Added yosys-smtbmc	2015-10-14 00:47:04 +02:00
Clifford Wolf	7bcd2a4bb3	Implemented smtbmc.py -i	2015-10-14 00:18:38 +02:00
Clifford Wolf	29160525aa	Added smtbmc.py	2015-10-13 17:17:23 +02:00
Clifford Wolf	3a22b31bda	Added write_smt2 -wires	2015-10-13 17:17:12 +02:00
Clifford Wolf	f42218682d	Added examples/ top-level directory	2015-10-13 15:41:20 +02:00
Clifford Wolf	f13e387321	SystemVerilog also has assume(), added implicit -D FORMAL	2015-10-13 14:21:20 +02:00
Clifford Wolf	34f34be17c	Merge branch 'master' of https://github.com/rubund/yosys	2015-10-13 11:01:19 +02:00
Clifford Wolf	eb1e3caae7	Fixed "flatten" for unconnected inout ports	2015-10-13 10:30:23 +02:00
Ruben Undheim	978933704b	Use DESTDIR as defined in https://www.gnu.org/prep/standards/html_node/DESTDIR.html ... This is needed for painless packaging of yosys	2015-10-11 00:56:20 +02:00
Ruben Undheim	2792b00792	Use LDFLAGS, CXXFLAGS and CPPFLAGS from the environment when building	2015-10-11 00:47:37 +02:00
Clifford Wolf	ba4cce9f19	Added support for "parameter" and "localparam" in global context	2015-10-07 14:59:08 +02:00
Clifford Wolf	e51dcc83d0	Fixed complexity of assigning to vectors in constant functions	2015-10-01 12:15:35 +02:00
Clifford Wolf	9caeadf797	Fixed detection of unconditional $readmem[hb]	2015-09-30 15:46:51 +02:00
Clifford Wolf	c58bd5dc30	Added edgetypes command	2015-09-27 11:53:20 +02:00
Clifford Wolf	281c1f4029	Some cleanups in qwp	2015-09-26 10:42:27 +02:00
Clifford Wolf	ddcfc99f8c	Added "test_cell -noeval"	2015-09-25 17:27:18 +02:00
Clifford Wolf	82028c42e0	Added wreduce $mul support and fixed signed $mul opt_const bug	2015-09-25 17:27:06 +02:00
Clifford Wolf	4864736167	Bugfix in bram read-enable code	2015-09-25 14:22:33 +02:00
Clifford Wolf	f9d7df0869	Bugfixes in $readmem[hb]	2015-09-25 13:49:48 +02:00
Clifford Wolf	4ac202e2a5	Bugfixes in writing of memories as Verilog	2015-09-25 13:49:26 +02:00
Clifford Wolf	b2544cfcf7	Fixed segfault in AstNode::asReal	2015-09-25 12:38:01 +02:00
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	ec92c89659	Added pivoting to qwp solver	2015-09-24 22:16:37 +02:00
Clifford Wolf	69071bbc5f	Improved qwp performance	2015-09-24 21:50:37 +02:00
Clifford Wolf	b1e9cb332d	Added statistics summary to "qwp"	2015-09-24 21:22:24 +02:00
Clifford Wolf	3501f8e364	Fixed memory_bram for ROMs in BRAMs with write-enable inputs	2015-09-24 11:37:15 +02:00
Clifford Wolf	1b8cb9940e	Fixed AstNode::mkconst_bits() segfault on zero-sized constant	2015-09-24 11:21:20 +02:00
Clifford Wolf	e2e092b144	Added read_verilog -nodpi	2015-09-23 08:23:38 +02:00
Clifford Wolf	089c1e176f	Bugfix in handling of multi-dimensional memories	2015-09-23 07:56:17 +02:00
Clifford Wolf	559929e341	Warning for $display/$write outside initial block	2015-09-23 07:16:03 +02:00
Clifford Wolf	b845b77f86	Fixed support for $write system task	2015-09-23 07:10:56 +02:00
Clifford Wolf	a3a13cce32	Fixed detection of "task foo(bar);" syntax error	2015-09-22 21:34:21 +02:00
Clifford Wolf	6176f4d081	Fixed multi-level prefix resolving	2015-09-22 20:52:02 +02:00
Clifford Wolf	4b8200eb49	Fixed segfault on invalid verilog constant 1'b_	2015-09-22 08:13:09 +02:00
Clifford Wolf	405cf67b64	Fixed emcc build	2015-09-21 12:33:36 +02:00