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17138 commits 142 branches 67 tags 50 MiB
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10 commits

Author SHA1 Message Date
Miodrag Milanovic
7fe32137bd Revert "Fix tests due to ABC improvements" 
This reverts commit 417e871b06.
 2026-05-11 14:47:08 +02:00
Miodrag Milanovic
ced2521b03 Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
Miodrag Milanovic
417e871b06 Fix tests due to ABC improvements 2026-03-30 15:23:27 +01:00
Miodrag Milanovic
602f3fd1a5 Add missing EOL 2026-03-06 09:10:55 +01:00
Miodrag Milanovic
52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Lofty
cd60dd4912 synth_analogdevices: update timing model and tests 2026-03-05 05:37:13 +00:00
Krystine Sherwin
5d3ed5a418 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-03-05 05:37:13 +00:00
Lofty
39cb61615f analogdevices: DSP inference 2026-03-05 05:37:12 +00:00
Krystine Sherwin
9be3cfb3f9 analogdevices: Update lutram.ys test 2026-03-05 05:37:12 +00:00
Lofty
6f205b41f5 test suite 2026-03-05 05:37:12 +00:00