Lofty
09dd419183
wip
2025-06-07 02:06:42 +01:00
Lofty
c7ab9f0300
wip
2025-06-06 11:04:38 +01:00
Joachim Strömbergson
90f50722ab
Change to blocking assignments in non-clocked process.
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2025-04-23 17:13:37 +02:00
Patrick Urban
61387d78b7
gatemate: Prevent implicit declaration of ram_{we,en}
2023-06-05 19:08:44 +02:00
Patrick Urban
2004a9ff4a
gatemate: Add CC_FIFO_40K simulation model
2023-05-30 09:06:23 +02:00
Patrick Urban
c244a7161b
gatemate: Fix SDP read behavior
2023-05-30 09:05:43 +02:00
Patrick Urban
2c7ba0e752
gatemate: Enable register initialization
2023-02-15 17:29:01 +01:00
Patrick Urban
4cb27b1a3a
gatemate: Ensure compatibility of LVDS ports with VHDL
2023-02-14 12:02:41 +01:00
gatecat
7c756c9959
gatemate: Add preliminary sim models for LUT tree structures
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-06-27 10:09:48 +01:00
Patrick Urban
cb41209095
synth_gatemate Revert cascade A/B port mixup
2021-11-13 21:53:25 +01:00
Patrick Urban
0d871b6c49
synth_gatemate: Add block RAM cascade support
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* add simulation model for block RAM cascade in 40K mode
* limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
2021-11-13 21:53:25 +01:00
Patrick Urban
74aee88e81
synth_gatemate: Remove specify blocks
2021-11-13 21:53:25 +01:00
Patrick Urban
4bee908ae8
synth_gatemate: Revise block RAM read modes and initialization
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* enable mixed read-width / write-width ports in SDP mode
* fix NO_CHANGE and WRITE_THROUGH behavior during read access
* remove redundant zero-initialization
* set A/B_WE bit during map (gatemate_bramopt pass could be removed later)
* differentiate "upper" and "lower" initialization for cascade mode
2021-11-13 21:53:25 +01:00
Patrick Urban
6825de6343
synth_gatemate: Registers are uninitialized
2021-11-13 21:53:25 +01:00
Patrick Urban
0a72952d5f
synth_gatemate: Apply review remarks
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* remove unused techmap models in `map_regs.v`
* replace RAM initilization loops with 320-bit-writes
* add script to test targets in top-level Makefile
* remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v`
* iterate over all modules in `gatemate_bramopt` pass
2021-11-13 21:53:25 +01:00
Patrick Urban
cfcc38582a
synth_gatemate: Apply review remarks
2021-11-13 21:53:25 +01:00
Patrick Urban
240d289fff
synth_gatemate: Initial implementation
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Signed-off-by: Patrick Urban <patrick.urban@web.de>
2021-11-13 21:53:25 +01:00
