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Code Activity
15685 commits 124 branches 59 tags 44 MiB
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2474 commits

Author SHA1 Message Date
Eddie Hung
dd8d264bf5 install *_nowide.lut files 2019-06-29 19:37:04 -07:00
Eddie Hung
728839d6ca Remove peepopt call in synth_xilinx since already in synth -run coarse 2019-06-28 12:53:38 -07:00
Eddie Hung
ea0f7c9be9 Restore $__XILINX_MUXF78 const optimisation 2019-06-28 12:12:41 -07:00
Eddie Hung
a193bf27c9 Clean up trimming leading 1'bx in A during techmappnig 2019-06-28 12:03:43 -07:00
Eddie Hung
cf020befeb Fix CARRY4 abc_box_id 2019-06-28 11:28:50 -07:00
Eddie Hung
4ef26d4755 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-28 11:09:42 -07:00
Eddie Hung
03705f69f4 Update synth_ice40 -device doc to be relevant for -abc9 only 2019-06-28 09:49:01 -07:00
Eddie Hung
3f87575cb6 Disable boxing of ECP5 dist RAM due to regression 2019-06-28 09:46:36 -07:00
Eddie Hung
0318860b93 Add write address to abc_scc_break of ECP5 dist RAM 2019-06-28 09:45:48 -07:00
Eddie Hung
b9ddee0c87 Fix DO4 typo 2019-06-28 09:45:40 -07:00
Eddie Hung
00f63d82ce Reduce diff with upstream 2019-06-27 16:13:22 -07:00
Eddie Hung
af8a5ae5fe Extraneous newline 2019-06-27 16:12:20 -07:00
Eddie Hung
4daa746797 Remove noise from ice40/cells_sim.v 2019-06-27 16:11:39 -07:00
Eddie Hung
9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung
312c03e4ca Remove redundant doc 2019-06-27 15:28:55 -07:00
Eddie Hung
4d00e27ed7 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-27 11:23:30 -07:00
Eddie Hung
1237a4c116 Add warning if synth_xilinx -abc9 with family != xc7 2019-06-27 11:22:49 -07:00
Eddie Hung
6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung
593e4a30bb MUXF78 -> $__MUXF78 to indicate internal 2019-06-26 20:09:28 -07:00
Eddie Hung
dbb8c8caaa Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 20:07:31 -07:00
Eddie Hung
4de25a1949 Add WE to ECP5 dist RAM's abc_scc_break too 2019-06-26 20:02:19 -07:00
Eddie Hung
a7a88109f5 Update comment on boxes 2019-06-26 20:00:15 -07:00
Eddie Hung
b7bef15b16 Add "WE" to dist RAM's abc_scc_break 2019-06-26 19:58:09 -07:00
Eddie Hung
b9ff0503f3 synth_xilinx's muxcover call to be very conservative -- -nodecode 2019-06-26 17:57:10 -07:00
Eddie Hung
f0a1726a1a Accidentally removed "simplemap $mux" 2019-06-26 17:48:49 -07:00
Eddie Hung
2b104ed6c8 Replace with <internal options> 2019-06-26 17:42:50 -07:00
Eddie Hung
cae69a3edd Rework help_mode for synth_xilinx -widemux 2019-06-26 17:41:21 -07:00
Eddie Hung
5f807a7a5b Return to upstream synth_xilinx with opt -full and wreduce 2019-06-26 16:25:48 -07:00
Eddie Hung
812469aaa3 Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux 2019-06-26 14:48:35 -07:00
Eddie Hung
c762be5930 Instead of blocking wreduce on $mux, use -keepdc instead #1132 2019-06-26 11:48:35 -07:00
Eddie Hung
8d8261c71f Do not call opt with -full before muxcover 2019-06-26 11:38:28 -07:00
Eddie Hung
80de03a7a6 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 11:24:39 -07:00
Eddie Hung
4d0014d1b1 Cleanup abc_box_id 2019-06-26 11:23:57 -07:00
Eddie Hung
612083a807 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 10:33:54 -07:00
Eddie Hung
5e1b8d458b Remove unused var 2019-06-26 10:33:07 -07:00
Eddie Hung
988e6163ab Add _nowide variants of LUT libraries in -nowidelut flows 2019-06-26 10:23:29 -07:00
Eddie Hung
741ebba70a Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-26 10:10:16 -07:00
Eddie Hung
799b18263f Merge branch 'koriakin/xc7nocarrymux' into xaig 2019-06-26 10:04:01 -07:00
Miodrag Milanovic
ea0b6258ab Simulation model verilog fix 2019-06-26 18:34:34 +02:00
Eddie Hung
4ce329aefd synth_ecp5 rename -nomux to -nowidelut, but preserve former 2019-06-26 09:33:48 -07:00
Eddie Hung
7389b043c0 Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux 2019-06-26 09:33:38 -07:00
Eddie Hung
177c26ca35 Rename -minmuxf to -widemux 2019-06-26 09:16:45 -07:00
Eddie Hung
184cfacfb5 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 09:15:28 -07:00
David Shah
0dd850e655 abc9: Add wire delays to synth_ice40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-26 11:39:44 +01:00
whitequark
3d4102cfa4 Add more ECP5 Diamond flip-flops. 
This includes all I/O registers, and a few more regular FFs where it
was convenient.
 2019-06-26 01:57:29 +00:00
Eddie Hung
480a04cb3c Realistic delays for RAM32X1D too 2019-06-25 09:34:28 -07:00
Eddie Hung
6095357390 Add RAM32X1D box info 2019-06-25 09:34:19 -07:00
Eddie Hung
6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
Eddie Hung
4238feed81 This optimisation doesn't seem to work... 2019-06-25 09:21:46 -07:00
Eddie Hung
158325956e Realistic delays for RAM32X1D too 2019-06-24 23:05:28 -07:00