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Merge remote-tracking branch 'origin/xaig' into xc7mux

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This commit is contained in:
Eddie Hung 2019-06-26 20:07:31 -07:00
commit dbb8c8caaa
7 changed files with 56 additions and 47 deletions
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5
techlibs/ecp5/abc_5g.box
View file

@ -4,8 +4,9 @@
# Box 1 : CCU2C (2xCARRY + 2xLUT4)
# Outputs: S0, S1, COUT
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
# input/output and bus has been moved
# there overriding the otherwise
# alphabetical ordering)
# name ID w/b ins outs
CCU2C 1 1 9 3

2
techlibs/ecp5/cells_sim.v
View file

@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule
// ---------------------------------------
(* abc_box_id=2, abc_scc_break="DI" *)
(* abc_box_id=2, abc_scc_break="DI,WRE" *)
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,

5
techlibs/xilinx/abc_xc7.box
View file

@ -23,8 +23,9 @@ MUXF78 3 1 6 1
# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
# input/output and the entire bus has been
# moved there overriding the otherwise
# alphabetical ordering)
CARRY4 4 1 10 8
482 - - - - 223 - - - 222
598 407 - - - 400 205 - - 334

6
techlibs/xilinx/cells_sim.v
View file

@ -289,7 +289,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
(* abc_box_id = 5, abc_scc_break="D" *)
(* abc_box_id = 5, abc_scc_break="D,WE" *)
module RAM32X1D (
output DPO, SPO,
input D, WCLK, WE,
@ -307,7 +307,7 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 6, abc_scc_break="D" *)
(* abc_box_id = 6, abc_scc_break="D,WE" *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
@ -325,7 +325,7 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 7, abc_scc_break="D" *)
(* abc_box_id = 7, abc_scc_break="D,WE" *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,