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yosys/techlibs
History
Eddie Hung b9ddee0c87 Fix DO4 typo
2019-06-28 09:45:40 -07:00
..
achronix Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
anlogic Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
common Make doc consistent 2019-06-14 10:32:46 -07:00
coolrunner2 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
easic Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
ecp5 Fix DO4 typo 2019-06-28 09:45:40 -07:00
gowin Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master 2019-04-22 09:09:27 +02:00
greenpak4 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
ice40 Extraneous newline 2019-06-27 16:12:20 -07:00
intel Fix formatting for synth_intel.cc 2019-05-09 08:40:05 -07:00
sf2 Add link to SF2 / igloo2 macro library guide 2019-03-07 09:08:26 -08:00
xilinx Reduce diff with upstream 2019-06-27 16:13:22 -07:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00