mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-20 23:56:38 +00:00
Code Activity
12782 commits 99 branches 53 tags 43 MiB
Commit graph

285 commits

Author SHA1 Message Date
Krystine Sherwin 7343ef159e
synth_quicklogic: Testing double_sync_ram_tdp 2023-12-04 11:17:18 +13:00
Krystine Sherwin 945e78e266
Adding double_sync_ram_tdp to blockram.v 2023-12-04 11:16:50 +13:00
Krystine Sherwin 2d6738bb10
qlf_tests: minor adjustment 
Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
 2023-12-04 09:38:48 +13:00
N. Engelhardt 1bd3678f75 remove example test 2023-12-01 14:28:50 +01:00
N. Engelhardt c2fc33f0eb fix test setup for synth_quicklogic memory tests 2023-12-01 14:03:07 +01:00
N. Engelhardt 190cbd54b1 fix test setup for synth_quicklogic memory tests 2023-12-01 10:47:39 +01:00
Krystine Sherwin 5634d98ccb
attempting to sim split memory tests 
and failing
 2023-12-01 21:16:58 +13:00
Krystine Sherwin d9d54e66c7
QLF_TDP36K: asymmetric simulation tests 2023-12-01 20:47:39 +13:00
Krystine Sherwin 0cd4a10c81
QLF_TDP36K: truncation tests matter 
Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
 2023-12-01 17:14:01 +13:00
Krystine Sherwin 7f90fafd15
QLF_TDP36K: more basic tdp/sdp sim tests 
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
 2023-12-01 17:00:15 +13:00
Krystine Sherwin 7a659bdd26
QLF_TDP36K: parameterised sim test gen 
Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
 2023-12-01 16:26:00 +13:00
Krystine Sherwin b62173775c
QLF_TDP36K: test bram_tdp post synth 2023-12-01 09:52:27 +13:00
N. Engelhardt 64609afe2c add example memory test 2023-11-30 19:35:43 +01:00
Krystine Sherwin f810bd88f5 quicklogic: wildcard asymmetric memory tests 2023-11-30 17:33:13 +01:00
Krystine Sherwin c54d6b29d3 tests: asymmetric sync rams now correctly asymmetric 
Also both use the same named parameters for better mirroring.
 2023-11-30 17:33:13 +01:00
Krystine Sherwin cdb20baf1f quicklogic: testing port widths on split rams 2023-11-30 17:33:13 +01:00
Krystine Sherwin 4c03c84fa7 quicklogic: testing 1:4 assymetric memory 2023-11-30 17:33:13 +01:00
Krystine Sherwin a1073c706e quicklogic: fix double width read 2023-11-30 17:33:13 +01:00
Krystine Sherwin fbf8607b97 quicklogic: Testing split TDP36K 
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
 2023-11-30 17:33:13 +01:00
Krystine Sherwin 0cd67ce473 quicklogic: Initial blockram tests 
Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
 2023-11-30 17:33:13 +01:00
Martin Povišer fb34167fd4 fixup! quicklogic: Add basic k6n10f tests 2023-11-30 13:43:56 +01:00
Martin Povišer d11a85fcba fixup! quicklogic: Add basic k6n10f tests 2023-11-30 11:12:55 +01:00
Martin Povišer 193144e68b fixup! quicklogic: Add basic k6n10f tests 2023-11-30 10:45:39 +01:00
Martin Povišer e70122b74e fixup! quicklogic: Add basic k6n10f tests 2023-11-29 11:20:16 +01:00
Martin Povišer 5bc587c843 quicklogic: Add k6n10f DSP test 2023-11-27 17:43:21 +01:00
Martin Povišer 502559cba4 quicklogic: Fix dffs.ys test 2023-11-27 17:27:46 +01:00
Martin Povišer a3b3333eeb quicklogic: Add basic k6n10f tests 2023-11-27 12:14:48 +01:00
Martin Povišer 74296e3d92 quicklogic: Move pp3 tests one level down 2023-11-27 12:05:55 +01:00
N. Engelhardt e230a871be synth_quicklogic: rearrange files to prepare for adding more architectures 2023-11-27 08:37:33 +01:00
Lofty 7ae4041e20 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
Lofty b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default" 2023-11-03 14:52:52 +00:00
Lofty 32082477b5 ice40, ecp5: enable ABC9 by default 2023-11-03 08:52:54 +00:00
Martin Povišer 62d6338688 quicklogic: Fix pp3 dffs test 
Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
 2023-10-12 12:45:40 +02:00
Miodrag Milanovic a42c630264 put back previous test state, due to default change 2023-08-29 10:21:58 +02:00
Miodrag Milanovic 3b9ebfa672 Addressed code review comments 2023-08-25 11:10:20 +02:00
Miodrag Milanovic ea50d96135 fixed tests 2023-08-23 10:54:29 +02:00
Miodrag Milanovic e6f7cf3b29 Update tests 2023-06-09 14:41:45 +02:00
Eddie Hung 862631d657 Add ABC9 DSP cascade test 2023-05-25 18:42:08 +01:00
Lofty 00b0e850db intel_alm: re-enable carry chains for ABC9 2023-05-25 18:28:10 +01:00
Ralf Fuest 30f1d10948 gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
Benjamin Barzen 8611429237
ABC9: Cell Port Bug Patch (#3670) 
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2023-04-22 16:24:36 -07:00
Miodrag Milanovic 0f5e7c244d add additional dff and lutram tests 2023-04-06 09:10:14 +02:00
Miodrag Milanovic 54d313efc3 add test for CCU2D 2023-04-06 09:10:14 +02:00
Miodrag Milanovic 61da330a38 Update tests 2023-03-20 09:58:41 +01:00
gatecat 2ab3747cc9 fabulous: Add support for mapping carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-27 09:50:34 +01:00
KrystalDelusion f80920bd9f Genericising bug1836.ys 2023-02-21 05:23:16 +13:00
KrystalDelusion 445a801a85 bug3205.ys removed 
Made redundant by TDP test(s) in memories.ys
 2023-02-21 05:23:16 +13:00
KrystalDelusion 51c2d476c2 Removing extra default_nettype lines 2023-02-21 05:23:16 +13:00
KrystalDelusion 8f6a06951c Fix for sync_ram_sdp not being final module 
Explicitly declare -top in synth_intel_alm.
 2023-02-21 05:23:16 +13:00
KrystalDelusion af1b9c9e07 Tests for ram_style = "huge" 
iCE40 SPRAM and Xilinx URAM
 2023-02-21 05:23:15 +13:00