141 commits

Author	SHA1	Message	Date
Miodrag Milanovic	c95b9b4ba5	Support memories in aiw and multiclock	2022-03-31 13:10:13 +02:00
Miodrag Milanovic	322ab1cd54	Proper SigBit forming in sim	2022-03-22 14:43:18 +01:00
Miodrag Milanovic	ff3b0c2c46	Proper SigBit forming in sim	2022-03-22 14:22:32 +01:00
Miodrag Milanovic	55eed8df57	More verbose warnings	2022-03-18 14:47:35 +01:00
Miodrag Milanovic	1f3423cd7d	Recognize registers and set initial state for them in tb	2022-03-16 14:35:39 +01:00
Miodrag Milanovic	e217e3017a	Update sim help message.	2022-03-16 07:55:57 +01:00
Miodrag Milanovic	f5c20b8286	Added fst2tb pass for generating testbench	2022-03-14 19:06:29 +01:00
Miodrag Milanović	cbece4af0c	Merge pull request #3229 from YosysHQ/micko/sim_date ... Add date parameter to enable full date/time and version info	2022-03-11 19:02:57 +01:00
Claire Xenia Wolf	e21badd4b3	Add "sim -q" option ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-03-11 16:26:11 +01:00
Miodrag Milanovic	37de369ba7	Add date parameter to enable full date/time and version info	2022-03-11 16:01:59 +01:00
Claire Xenia Wolf	be32de1caa	Small fix in "sim" help message ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-03-11 15:36:23 +01:00
Miodrag Milanovic	5204694123	FstData already do conversion to VCD	2022-03-11 15:21:36 +01:00
Miodrag Milanovic	b72c779204	Support cell name in btor witness file	2022-03-11 15:11:14 +01:00
Miodrag Milanovic	357336339a	Proper write of memory data	2022-03-11 11:19:53 +01:00
Miodrag Milanovic	295b0d1899	Start work on memory init	2022-03-09 18:34:02 +01:00
Miodrag Milanovic	f37ac5d934	Fixes and error check	2022-03-09 09:48:29 +01:00
Miodrag Milanovic	ede348cdc2	cleanup	2022-03-07 16:32:32 +01:00
Miodrag Milanovic	1b1ecd4ab0	Error checks for aiger witness	2022-03-07 15:00:14 +01:00
Miodrag Milanovic	b6aca1d743	btor2 witness co-simulation	2022-03-07 13:59:36 +01:00
Miodrag Milanović	9581b9adac	Merge pull request #3219 from YosysHQ/micko/quick_vcd ... VCD reader support by using external tool	2022-03-04 10:42:14 +01:00
Miodrag Milanovic	59983eda17	Add option to ignore X only signals in output	2022-03-02 16:02:13 +01:00
Miodrag Milanovic	48b56a4f7f	Write simulation files after simulation is performed	2022-03-02 15:23:07 +01:00
Miodrag Milanovic	28bc88a57e	Cleanup	2022-03-02 09:39:22 +01:00
Miodrag Milanovic	94505395a9	Refactor sim output writers	2022-02-28 18:22:39 +01:00
Miodrag Milanovic	dfd4c81eac	Quick fix	2022-02-28 11:40:06 +01:00
Claire Xenia Wolf	56b968f61c	Add writing of aiw files to "sim" command ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-02-28 10:50:08 +01:00
Claire Xenia Wolf	1fd3a642c9	Hotfix in AIGER witness reader state machine ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-02-28 10:41:44 +01:00
Miodrag Milanovic	8be09b5b24	VCD reader support by using external tool	2022-02-28 09:09:07 +01:00
Miodrag Milanovic	9571acc0bf	Support extended aiw format	2022-02-27 16:37:40 +01:00
Miodrag Milanovic	fca168797e	Fix for last clock edge data	2022-02-25 16:15:32 +01:00
Claire Xenia Wolf	ca261d3c28	Experimental sim changes	2022-02-25 16:02:06 +01:00
Claire Xen	a41c1df76f	Merge pull request #3211 from YosysHQ/micko/witness ... Add support for AIGER witness files in "sim" command	2022-02-22 16:22:06 +01:00
Miodrag Milanovic	fd3f08753a	Fix handling of ce_over_srst	2022-02-21 16:36:12 +01:00
Claire Xenia Wolf	1aa9ad25d0	Fix cycle 0 in aiger witness co-simulation ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2022-02-18 16:27:41 +01:00
Miodrag Milanovic	41754b4207	Added AIGER witness file co simulation	2022-02-18 15:04:02 +01:00
Miodrag Milanovic	13a5c28459	simplify logic of handling flip-flops and latches	2022-02-18 09:17:36 +01:00
Miodrag Milanovic	61752b255f	Review cleanup	2022-02-17 17:18:36 +01:00
Miodrag Milanovic	fb22d7cdc4	Add support for various ff/latch cells simulation	2022-02-16 13:27:59 +01:00
Miodrag Milanović	d7f7227ce8	Merge pull request #3185 from YosysHQ/micko/co_sim ... Add co-simulation in sim pass	2022-02-07 16:36:43 +01:00
Miodrag Milanovic	c0a156bcb4	Error detection for co-simulation	2022-02-04 11:11:36 +01:00
Miodrag Milanovic	6db23de7b1	bug fix and cleanups	2022-02-04 10:01:06 +01:00
Miodrag Milanovic	990aee5531	respect hide_internal flag	2022-02-02 10:15:22 +01:00
Miodrag Milanovic	169ffcd2fb	unify cycles counting and cleanup	2022-02-02 10:08:23 +01:00
Miodrag Milanovic	820b2fdd65	added stimulus mode and param check	2022-02-02 09:37:32 +01:00
Miodrag Milanovic	8ba2000a50	error when no signal found	2022-01-31 17:41:50 +01:00
Miodrag Milanovic	1b5ff92e62	Cleanup	2022-01-31 13:45:28 +01:00
Miodrag Milanovic	eabd0ff115	Compare bits when not all are defined	2022-01-31 13:41:02 +01:00
Miodrag Milanovic	26de52fa09	Cleanup	2022-01-31 12:00:15 +01:00
Miodrag Milanovic	6513300db7	message update	2022-01-31 11:41:52 +01:00
Miodrag Milanovic	543feb75cb	Display simulation time data	2022-01-31 10:52:47 +01:00