Emil J. Tywoniak
8b6049a220
quicklogic: fix dspv2 tests
2025-03-06 18:00:53 +01:00
Emil J. Tywoniak
b420951e6c
quicklogic: rename dspv1 full synth_quicklogic test for clarity
2025-03-06 17:59:46 +01:00
Emil J. Tywoniak
7e3122848f
quicklogic: ql_dsp_simd add dspv1 test
2025-03-06 12:56:11 +01:00
Emil J. Tywoniak
6e1ba9206f
quicklogic: remove irrelevant comments in dspv2 test
2025-03-06 12:55:56 +01:00
Emil J. Tywoniak
a8c10eea03
quicklogic: ql_dsp_simd add dspv2 support, fix dspv1
2025-03-06 11:25:01 +01:00
Emil J. Tywoniak
30473c4899
synth_quicklogic: enable dspv2 tests, fix -dspv2
2025-02-27 17:41:57 +01:00
Emil J. Tywoniak
402ca82503
synth_quicklogic: add -dspv2 to opt into v2 DSP blocks
2025-02-27 17:41:57 +01:00
Martin Povišer
fa8fc08621
qlf_k6n10f: Start tests
2025-02-20 11:30:29 +01:00
Emil J. Tywoniak
6240aec433
test: restore verific handling, nicer naming
2024-12-13 10:24:47 +01:00
Martin Povišer
ca5c2fdff1
quicklogic: Relax the LUT number test
2024-10-07 15:27:03 +02:00
Lofty
13ecbd5c76
quicklogic: test that dividing by a constant does not infer carry chains
2024-10-03 20:05:28 +01:00
Miodrag Milanovic
0c7ac36dcf
Add workflows and CODEOWNERS and fixed gitignore
2024-04-11 14:56:00 +02:00
Jannis Harder
331ac5285f
tests: Run async2sync before sat and/or sim to handle $check cells
...
Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.
While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.
2024-02-01 16:14:11 +01:00
Martin Povišer
22cc4aff51
quicklogic: Test TDP36K inference with initial data
2023-12-04 15:52:03 +01:00
Krystine Sherwin
e5c32f399a
synth_quicklogic: Testing double_sync_ram_tdp
2023-12-04 15:52:03 +01:00
Krystine Sherwin
215a777eb3
qlf_tests: minor adjustment
...
Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
2023-12-04 15:52:03 +01:00
N. Engelhardt
33ca6994b7
remove example test
2023-12-04 15:52:03 +01:00
N. Engelhardt
3c5b0ab164
fix test setup for synth_quicklogic memory tests
2023-12-04 15:52:03 +01:00
Krystine Sherwin
509d176523
attempting to sim split memory tests
...
and failing
2023-12-04 15:52:03 +01:00
Krystine Sherwin
0d1668c1ee
QLF_TDP36K: asymmetric simulation tests
2023-12-04 15:52:03 +01:00
Krystine Sherwin
497cd021af
QLF_TDP36K: truncation tests matter
...
Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
7f12d0ba95
QLF_TDP36K: more basic tdp/sdp sim tests
...
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
2023-12-04 15:52:03 +01:00
Krystine Sherwin
3d08ed216d
QLF_TDP36K: parameterised sim test gen
...
Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ba3be3fd1c
QLF_TDP36K: test bram_tdp post synth
2023-12-04 15:52:03 +01:00
N. Engelhardt
f9c8978128
add example memory test
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ede4eaeee2
quicklogic: wildcard asymmetric memory tests
2023-12-04 15:52:03 +01:00
Krystine Sherwin
ba09866217
quicklogic: testing port widths on split rams
2023-12-04 15:52:03 +01:00
Krystine Sherwin
1a843b2a86
quicklogic: testing 1:4 assymetric memory
2023-12-04 15:52:03 +01:00
Krystine Sherwin
7513bfcbfe
quicklogic: fix double width read
2023-12-04 15:52:03 +01:00
Krystine Sherwin
8d3b238b9b
quicklogic: Testing split TDP36K
...
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
2023-12-04 15:52:03 +01:00
Krystine Sherwin
991850e1c9
quicklogic: Initial blockram tests
...
Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
2023-12-04 15:52:03 +01:00
Martin Povišer
a5c8d246f7
quicklogic: Add k6n10f DSP test
2023-12-04 15:52:03 +01:00
Martin Povišer
db9e5b4f14
quicklogic: Fix dffs.ys test
2023-12-04 15:52:03 +01:00
Martin Povišer
554d8caef7
quicklogic: Add basic k6n10f tests
2023-12-04 15:52:03 +01:00
Martin Povišer
6672b6c1b3
quicklogic: Move pp3 tests one level down
2023-12-04 15:52:02 +01:00
N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
Martin Povišer
62d6338688
quicklogic: Fix pp3 dffs test
...
Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
2023-10-12 12:45:40 +02:00
Lofty
dce037a62c
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
Marcelina Kościelnicka
4a35f244aa
quicklogic: Add .gitignore file for test outputs.
2021-03-23 17:35:00 +01:00
Lofty
f4298b057a
quicklogic: PolarPro 3 support
...
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
