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Code Activity
15811 commits 122 branches 59 tags 72 MiB
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58 commits

Author SHA1 Message Date
Joachim Strömbergson
e4d6781088
Changing non clocked alway assignment to blocking. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2025-04-23 16:59:53 +02:00
gatecat
266f81816b ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-06 10:18:48 +01:00
Miodrag Milanovic
db367bd69e Add iopad_external_pin to some basic io primitives 2023-03-20 09:17:22 +01:00
Rick Luiken
414dc25a96 Add missing parameters for ecp5 2022-04-25 15:31:41 +01:00
Marcelina Kościelnicka
d0f4d0b153 ecp5: Do not use specify in generate in cells_sim.v. 2022-02-21 17:52:31 +01:00
Marcelina Kościelnicka
ac2bb70b52 ecp5: Fix DPR16X4 sim model. 2022-02-09 09:02:13 +01:00
Eddie Hung
8cda29137e ecp5: TRELLIS_FF bypass path only in async mode 2020-05-14 10:33:56 -07:00
Eddie Hung
a323881e15 xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells 2020-05-14 10:33:56 -07:00
Eddie Hung
a52f779eca ecp5: (* abc9_flop *) gated behind YOSYS 2020-05-14 10:33:56 -07:00
Eddie Hung
34c7732642 ecp5: add synth_ecp5 -dff to work with -abc9 2020-05-14 10:33:56 -07:00
Eddie Hung
d2284715fa ecp5: remove small LUT entries 2020-02-27 10:17:29 -08:00
Eddie Hung
46a89d7264 ecp5: deprecate abc9_{arrival,required} and *.{lut,box} 2020-02-27 10:17:29 -08:00
Eddie Hung
71906fab51 Nitpick cleanup for ecp5 2019-12-27 16:57:08 -08:00
Eddie Hung
aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung
2fa3857963 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-09-02 12:13:44 -07:00
Miodrag Milanovic
a3c16a0565 Fix TRELLIS_FF simulation model 2019-08-31 11:12:06 +02:00
Eddie Hung
f0fef90e9d Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 10:30:46 -07:00
David Shah
91b46ed816 ecp5: Add simulation equivalence check for Diamond FF implementations 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-30 13:27:36 +01:00
whitequark
d9c621f9d1 ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives. 2019-08-30 10:05:09 +00:00
whitequark
6fa8ce93e6 ecp5: add missing FD primitives. 2019-08-30 09:54:48 +00:00
whitequark
7e2825a2a4 ecp5: fix CEMUX on IFS/OFS primitives. 2019-08-30 09:42:33 +00:00
Eddie Hung
455da57272 Fix spacing 2019-08-23 13:21:21 -07:00
Eddie Hung
d672b1ddec Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-23 11:26:55 -07:00
Eddie Hung
a270af00cc Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
Eddie Hung
d46dc9c5b4 ecp5 to use -max_iter 1 2019-08-20 19:18:36 -07:00
Eddie Hung
55acf3120f ecp5 to use abc_map.v and _unmap.v 2019-08-20 18:59:03 -07:00
Eddie Hung
d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00
Eddie Hung
1c57b1e7ea Update abc_* attr in ecp5 and ice40 2019-08-16 15:56:57 -07:00
David Shah
a36fd8582e ecp5: Make cells_sim.v consistent with nextpnr 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:19:31 +01:00
Eddie Hung
3f87575cb6 Disable boxing of ECP5 dist RAM due to regression 2019-06-28 09:46:36 -07:00
Eddie Hung
0318860b93 Add write address to abc_scc_break of ECP5 dist RAM 2019-06-28 09:45:48 -07:00
Eddie Hung
9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung
6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung
4de25a1949 Add WE to ECP5 dist RAM's abc_scc_break too 2019-06-26 20:02:19 -07:00
Eddie Hung
4fadb471a3 Re-enable dist RAM boxes for ECP5 2019-06-24 22:12:50 -07:00
Eddie Hung
a4a7e63d84 Revert "Re-enable dist RAM boxes for ECP5" 
This reverts commit ca0225fcfa.
 2019-06-24 22:10:28 -07:00
Eddie Hung
ca0225fcfa Re-enable dist RAM boxes for ECP5 2019-06-24 21:55:54 -07:00
Eddie Hung
94314ae2d5 Comment out dist RAM boxing on ECP5 for now 2019-06-14 10:42:30 -07:00
Eddie Hung
ee428f73ab Remove WIP ABC9 flop support 2019-06-14 10:37:52 -07:00
David Shah
9566573054 ecp5: Add abc9 option 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-14 17:15:02 +01:00
Miodrag Milanovic
ca2b3feed8 Fix ECP5 cells_sim for iverilog 2019-03-01 19:25:23 +01:00
Clifford Wolf
41e5028f98
Merge pull request #794 from daveshah1/ecp5improve 
ECP5 Improvements
 2019-02-28 14:46:56 -08:00
Larry Doolittle
61fc411c5d Clean up some whitepsace outliers 2019-02-26 09:39:46 -08:00
David Shah
fa2f595cfa ecp5: Compatibility with Migen AsyncResetSynchronizer 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-25 13:24:30 +00:00
David Shah
ee8c9e854f ecp5: Add LSRMODE to flipflops for PRLD support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-21 12:35:22 +00:00
David Shah
1f51332808 ecp5: Adding some blackbox cells 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-07 14:56:38 +00:00
David Shah
d29b517fef ecp5: Sim model fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 15:16:40 +01:00
David Shah
983fb7ff88 ecp5: First BRAM type maps successfully 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:35:19 +01:00
David Shah
2ef1af8b58 ecp5: Script for BRAM IO connections 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:11:00 +01:00
David Shah
346cbbdbdc ecp5: Adding BRAM initialisation and config 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-09 14:19:04 +01:00