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rtlil: remove textual RTLIL reference tests for ease of maintenance
This commit is contained in:
Emil J. Tywoniak
parent
85bcdee232
commit
0d8c21129f
3 changed files with 0 additions and 1485 deletions
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@ -1,283 +0,0 @@
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autoidx 15
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attribute \src "everything.v:1.1-32.10"
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attribute \cells_not_processed 1
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module \alu
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attribute \src "everything.v:2.8-2.11"
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wire input 1 \clk
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attribute \src "everything.v:3.14-3.15"
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wire width 8 input 2 \A
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attribute \src "everything.v:4.14-4.15"
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wire width 8 input 3 \B
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attribute \src "everything.v:5.14-5.23"
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wire width 4 input 4 \operation
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attribute \src "everything.v:6.19-6.25"
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wire width 8 output 5 \result
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attribute \src "everything.v:7.13-7.15"
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wire output 6 \CF
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attribute \src "everything.v:8.13-8.15"
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wire output 7 \ZF
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attribute \src "everything.v:9.13-9.15"
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wire output 8 \SF
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attribute \src "everything.v:15.12-15.15"
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wire width 9 \tmp
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attribute \src "everything.v:17.2-31.5"
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wire width 8 $0\result[7:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\CF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\ZF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\SF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire width 9 $0\tmp[8:0]
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attribute \src "everything.v:17.2-31.5"
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wire width 9 $1\tmp[8:0]
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attribute \src "everything.v:21.11-21.16"
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wire width 9 $add$everything.v:21$2_Y
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attribute \src "everything.v:23.11-23.16"
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wire width 9 $sub$everything.v:23$3_Y
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attribute \src "everything.v:27.9-27.22"
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wire $eq$everything.v:27$4_Y
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attribute \src "everything.v:21.11-21.16"
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cell $add $add$everything.v:21$2
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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connect \A \A
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connect \B \B
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connect \Y $add$everything.v:21$2_Y
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end
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attribute \src "everything.v:23.11-23.16"
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cell $sub $sub$everything.v:23$3
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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connect \A \A
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connect \B \B
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connect \Y $sub$everything.v:23$3_Y
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end
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attribute \src "everything.v:27.9-27.22"
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cell $eq $eq$everything.v:27$4
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 32
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parameter \Y_WIDTH 1
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connect \A $1\tmp[8:0] [7:0]
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connect \B 0
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connect \Y $eq$everything.v:27$4_Y
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end
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attribute \src "everything.v:17.2-31.5"
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process $proc$everything.v:17$1
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assign { } { }
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assign { } { }
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assign { } { }
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assign { } { }
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assign { } { }
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assign $0\tmp[8:0] $1\tmp[8:0]
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assign $0\CF[0:0] $1\tmp[8:0] [8]
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assign $0\ZF[0:0] $eq$everything.v:27$4_Y
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assign $0\SF[0:0] $1\tmp[8:0] [7]
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assign $0\result[7:0] $1\tmp[8:0] [7:0]
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attribute \src "everything.v:19.3-24.10"
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switch \operation
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attribute \src "everything.v:19.19-19.19"
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case 4'0000
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assign { } { }
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assign $1\tmp[8:0] $add$everything.v:21$2_Y
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attribute \src "everything.v:21.17-21.17"
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case 4'0001
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assign { } { }
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assign $1\tmp[8:0] $sub$everything.v:23$3_Y
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case
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assign $1\tmp[8:0] \tmp
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end
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sync posedge \clk
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update \result $0\result[7:0]
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update \CF $0\CF[0:0]
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update \ZF $0\ZF[0:0]
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update \SF $0\SF[0:0]
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update \tmp $0\tmp[8:0]
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end
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end
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attribute \src "everything.v:34.1-40.10"
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attribute \cells_not_processed 1
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module \foo
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attribute \src "everything.v:35.17-35.18"
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wire width 8 input 1 \a
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attribute \src "everything.v:35.32-35.33"
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wire width 8 input 2 \b
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attribute \src "everything.v:35.48-35.49"
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wire width 8 output 3 \y
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attribute \src "everything.v:37.16-37.18"
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wire width 8 \bb
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attribute \src "everything.v:39.16-39.22"
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wire width 8 $add$everything.v:39$5_Y
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attribute \src "everything.v:39.16-39.22"
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cell $add $add$everything.v:39$5
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 8
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connect \A \a
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connect \B \bb
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connect \Y $add$everything.v:39$5_Y
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end
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connect \b \bb
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connect \y $add$everything.v:39$5_Y
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end
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attribute \cells_not_processed 1
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attribute \src "everything.v:1.1-32.10"
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module \zzz
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attribute \src "everything.v:27.9-27.22"
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wire $eq$everything.v:27$4_Y
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attribute \src "everything.v:23.11-23.16"
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wire width 9 $sub$everything.v:23$3_Y
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attribute \src "everything.v:21.11-21.16"
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wire width 9 $add$everything.v:21$2_Y
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attribute \src "everything.v:17.2-31.5"
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wire width 9 $1\tmp[8:0]
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attribute \src "everything.v:17.2-31.5"
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wire width 9 $0\tmp[8:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\SF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\ZF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire $0\CF[0:0]
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attribute \src "everything.v:17.2-31.5"
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wire width 8 $0\result[7:0]
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attribute \src "everything.v:15.12-15.15"
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wire width 9 \tmp
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attribute \src "everything.v:9.13-9.15"
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wire output 8 \SF
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attribute \src "everything.v:8.13-8.15"
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wire output 7 \ZF
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attribute \src "everything.v:7.13-7.15"
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wire output 6 \CF
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attribute \src "everything.v:6.19-6.25"
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wire width 8 output 5 \result
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attribute \src "everything.v:5.14-5.23"
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wire width 4 input 4 \operation
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attribute \src "everything.v:4.14-4.15"
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wire width 8 input 3 \B
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attribute \src "everything.v:3.14-3.15"
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wire width 8 input 2 \A
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attribute \src "everything.v:2.8-2.11"
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wire input 1 \clk
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wire $procmux$8_CMP
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wire width 9 $procmux$7_Y
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wire $procmux$9_CMP
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attribute \src "everything.v:27.9-27.22"
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cell $logic_not $eq$everything.v:27$4
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parameter \A_SIGNED 0
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parameter \Y_WIDTH 1
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parameter \A_WIDTH 8
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connect \A $1\tmp[8:0] [7:0]
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connect \Y $eq$everything.v:27$4_Y
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end
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attribute \src "everything.v:23.11-23.16"
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cell $sub $sub$everything.v:23$3
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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connect \A \A
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connect \B \B
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connect \Y $sub$everything.v:23$3_Y
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end
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attribute \src "everything.v:21.11-21.16"
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cell $add $add$everything.v:21$2
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 8
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parameter \B_WIDTH 8
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parameter \Y_WIDTH 9
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connect \A \A
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connect \B \B
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connect \Y $add$everything.v:21$2_Y
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end
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attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10"
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attribute \full_case 1
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cell $eq $procmux$8_CMP0
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parameter \A_SIGNED 0
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parameter \B_SIGNED 0
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parameter \A_WIDTH 4
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parameter \B_WIDTH 4
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parameter \Y_WIDTH 1
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connect \A \operation
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connect \B 4'0001
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connect \Y $procmux$8_CMP
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end
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attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10"
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attribute \full_case 1
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cell $pmux $procmux$7
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parameter \WIDTH 9
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parameter \S_WIDTH 2
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connect \A \tmp
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connect \B { $add$everything.v:21$2_Y $sub$everything.v:23$3_Y }
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connect \S { $procmux$9_CMP $procmux$8_CMP }
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connect \Y $procmux$7_Y
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end
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attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10"
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attribute \full_case 1
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cell $logic_not $procmux$9_CMP0
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parameter \A_SIGNED 0
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parameter \Y_WIDTH 1
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parameter \A_WIDTH 4
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connect \A \operation
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connect \Y $procmux$9_CMP
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end
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attribute \src "everything.v:17.2-31.5"
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cell $dff $procdff$10
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parameter \WIDTH 8
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parameter \CLK_POLARITY 1'1
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connect \D $procmux$7_Y [7:0]
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connect \Q \result
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connect \CLK \clk
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end
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attribute \src "everything.v:17.2-31.5"
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cell $dff $procdff$11
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parameter \WIDTH 1
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parameter \CLK_POLARITY 1'1
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connect \D $procmux$7_Y [8]
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connect \Q \CF
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connect \CLK \clk
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end
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attribute \src "everything.v:17.2-31.5"
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cell $dff $procdff$12
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parameter \WIDTH 1
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parameter \CLK_POLARITY 1'1
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connect \D $eq$everything.v:27$4_Y
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connect \Q \ZF
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connect \CLK \clk
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end
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attribute \src "everything.v:17.2-31.5"
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cell $dff $procdff$13
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parameter \WIDTH 1
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parameter \CLK_POLARITY 1'1
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connect \D $procmux$7_Y [7]
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connect \Q \SF
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connect \CLK \clk
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end
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attribute \src "everything.v:17.2-31.5"
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cell $dff $procdff$14
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parameter \WIDTH 9
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parameter \CLK_POLARITY 1'1
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connect \D $procmux$7_Y
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connect \Q \tmp
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connect \CLK \clk
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end
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connect $0\result[7:0] $1\tmp[8:0] [7:0]
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connect $0\SF[0:0] $1\tmp[8:0] [7]
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connect $0\ZF[0:0] $eq$everything.v:27$4_Y
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connect $0\CF[0:0] $1\tmp[8:0] [8]
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connect $0\tmp[8:0] $1\tmp[8:0]
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connect $1\tmp[8:0] $procmux$7_Y
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end
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@ -17,7 +17,6 @@ remove_empty_lines temp/roundtrip-text.write.il
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# Trim first line ("Generated by Yosys ...")
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tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il
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diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il
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diff temp/roundtrip-text.dump.il roundtrip-text.ref.il
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# Loading and writing it out again doesn't change the RTLIL
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$YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il"
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@ -30,10 +29,3 @@ $YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil
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remove_empty_lines temp/roundtrip-text.reload-hash.il
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tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il
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diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il
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echo "Without ABC, we don't get any irreproducibility and can pin that"
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echo "Has this test case started failing for you? Consider updating the reference"
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$YS -p "read_verilog -sv everything.v; synth -relativeshare -noabc; write_rtlil temp/roundtrip-text.synth.il"
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remove_empty_lines temp/roundtrip-text.synth.il
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tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il
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diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il
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